Have your tried completely rolling back the version of the interface, way back to 1.0 where we didn't have the interrupt or PS2 keyboard interface...
Not yet, but I'm pretty confident the PS2 (and by extension the interrupt request) sections of HDL in the Z80_bridge aren't interfering with anything else. There is no PS2 HDL to handle and read the PS2 input (there's no PS2 connector on the board at the moment), but I've attached a GND to the PS2_RDY input on the Z80_bridge just to be sure - but even if it did float HIGH, it wouldn't do anything except read PS2_DAT into a register anyway, ready to be read by an IO RD from the Z80.
I'm fairly convinced it's a bad IO on the FPGA. I've done my best to try and get some data from the 245_DIR line between pin 143 on the FPGA and pin 1 on the 74LVC245, but I'm finding attaching a logic analyser probe impossible - I need four or five arms to hold everything in place and operate the PC at the same time.
What I did do was a
very tight loop of test code:
6000 LD HL,0C000H ; Translates to GPU RAM address 0x0000
6003 LD A,(HL) ; Read a byte from GPU RAM into the accumulator
6004 LD A,(HL)
6005 LD A,(HL)
6006 LD A,(HL)
6007 LD A,(HL)
6008 JP 6003 ; Jump back and read again
Basically, it gets the Z80 to read an address in GPU RAM (pointed to by HL) several times and loop back to read it again constantly. Without looking at the clock timings for the individual commands I was using, I'd say it would be fair to estimate that the 245_DIR line should have been HIGH for anything between 20-40% of the time in that loop (disclaimer: wild guess from top of my head, but supported by
some logic). As all I could reliably connect to the 245's pin 1 was my multimeter, I would have expected to see something like 1V maybe, displayed as an average on the meter if it was working properly.
At rest (i.e. no GPU RAM access by the Z80), the pin read around 40mV. Whilst the test loop was running, it read 49-60mV, sometimes jumping to around 200mV, but it didn't seem to like being measured and I could hear some faint static from the speaker briefly, then it locked up entirely. I'm fairly confident that the test was sensitive enough to pick up if the line was going HIGH as it should do when the Z80 read the GPU RAM, but there was little sign of that. Very strange behaviour.
Naturally, I'd prefer to get the logic analyser to record 245_DIR during a GPU RAM RD transaction, but I just can't seem to get a logic probe to contact securely with pin 1 of the TSSOP. Might try soldering a wire to it later and try again.
My last step is a little extreme, so I'm holding off doing it until I'm happy I've exhausted all attempts with the logic analyser and I've had the time to dig out the oscilloscope and set it up (again, I need five arms and plenty of time to do that). Basically, I'll cut the 245_DIR trace and connect a spare FPGA IO (I have a couple) to the 245 with some wire-wrap, if need be.