FPGA VGA Controller for 8-bit computer

[nockieboy]

Right off the bat, with 7 layers, if he uses 1 graphics layer, he has another 6 layers for sprites, he can make an authentic hi-res version on games like PacMan.  4 colors for the hires background maze & pellets, and 4 or 16 colors for the player sprites.  Or he can use a colored font layer for the background.

All I need is another 48 hours in the day, and I'll be set! 

[BrianHG]

Playing around with the Z80 code now and 'colouring-in' lots of the output has made me realise how restrictive my MMU is.  4x16KB areas just isn't cutting it anymore - especially if I want to get the GPU running with CP/M; I'm going to have to make it more fine-grained.  I'm halfway through designing a much more flexible MMU in hardware, but I haven't touched that since I started down this FPGA GPU route a couple of months ago - now I'm thinking that I might as well build the MMU into the FPGA, seeing as it has access to (nearly) all the address lines it needs and some spare RAM space. I'm running out of IOs on this dev board though! 

PS2 keyboard is next, and whenever @jhpadjustable is up for it, perhaps some sound. 

Can't use simple page-able ram?  You'll get 256 pages of 64kb.  Simple enough to implement in the FPGA, or anywhere else.  Though, I'm not sure about your Z80 code & you will need to reserve a memory location for the paging.  You can also have 2 paging spaces, 1 for executable code and 1 for program data, though, some of the advance features of the Z80 instruction set wont be able to cross page boundaries on their own.

[nockieboy]

Playing around with the Z80 code now and 'colouring-in' lots of the output has made me realise how restrictive my MMU is.  4x16KB areas just isn't cutting it anymore - especially if I want to get the GPU running with CP/M; I'm going to have to make it more fine-grained.  I'm halfway through designing a much more flexible MMU in hardware, but I haven't touched that since I started down this FPGA GPU route a couple of months ago - now I'm thinking that I might as well build the MMU into the FPGA, seeing as it has access to (nearly) all the address lines it needs and some spare RAM space. I'm running out of IOs on this dev board though! 

PS2 keyboard is next, and whenever @jhpadjustable is up for it, perhaps some sound. 

Can't use simple page-able ram?  You'll get 256 pages of 64kb.  Simple enough to implement in the FPGA, or anywhere else.  Though, I'm not sure about your Z80 code & you will need to reserve a memory location for the paging.  You can also have 2 paging spaces, 1 for executable code and 1 for program data, though, some of the advance features of the Z80 instruction set wont be able to cross page boundaries on their own.

I'll just extend the same system I'm using now from reading A14-A15 and outputting EA14-EA21 to reading A12-A15 and outputting EA12-EA21 to break the banks down to smaller sizes. No issues crossing boundaries - the Z80 just sees 64KB of contiguous RAM, it doesn't know (or care) that the RAM could be made up of banks of RAM from all over a much larger physical memory space.

I'm designing a PCB for the 'next-level' dev board at the moment - it'll fit directly onto my computer and eliminate all the wiring, breadboards and dev board I'm currently contending with.  It'll basically be a v1 final board, but will have perhaps more IO considerations than the final board needs (for testing/developing an SD interface, etc).  For one, I'm looking to replace a couple of the 373 level converters on the address bus with 245s so I have the option of driving the expanded address bus from the FPGA - the FPGA will be able to fulfil the MMU's role if I decide to go that route, without any wiring, connection or PCB changes.  Will just need to modify the memory cards slightly to cater for the changes in A13/A12 being driven instead by EA13/EA12 from the FPGA etc.

I'm going to stick with Cyclone IV's for the moment as I have the dev environment set up for them - the above board will either use an EP4CE10 or CE15 FPGA, so the RAM will jump to 51 or 77KB respectively (and logic gate numbers increase respectively), but the package remains an easy-to-solder LQFP-144, minimising risk of problems/cost whilst I learn how to solder BGAs. 

[BrianHG]

For the future, the Lattice chip has 6x6 more pins than this chip Louis Rossmann is repairing in this video.



The secret here is the cleaning tinning of the pads and all that flux which helps transport the heat.
And a new PCB would be 100x cleaner than that water damaged mac.

Do not got to the 30$ lattice chip, that one has it's solder balls at 0.5mm instead of 0.8mm.  But, if you do got that route and have your PCB manufacturer place the BGA for you, you will have 4megabits of graphics memory.

30$ part: https://www.mouser.com/ProductDetail/Lattice/LFE5U-85F-6MG285C?utm_term=LFE5U-85F&qs=Rp3RbKSfAt3i%252b4nmoAgpiw%3D%3D&utm_campaign=LFE5U-85F-6MG285C&utm_medium=aggregator&utm_source=findchips&utm_content=Lattice

This one would need research on how to build a PCB with larger vias for cheap mode with larger, but, you use so few IO, all the core VCC&GNDs would be shared and the outer edge IOs would be the only ones in use.

The 0.8mm 2megabit part should be easy peasy.

Also, if you want a 240pin QFP, these Cyclone III exist:
https://www.aliexpress.com/item/33040049112.html?spm=a2g0o.productlist.0.0.1fb0572cf1SudS&algo_pvid=c9decdb7-cb39-4c61-a5e7-e7d7fb87dbaa&algo_expid=c9decdb7-cb39-4c61-a5e7-e7d7fb87dbaa-15&btsid=29a7fbad-6c65-48e0-acb4-eb26363f6e85&ws_ab_test=searchweb0_0,searchweb201602_7,searchweb201603_55

You will get 1 megabit.  My project runs your GPU on an Cyclone EP3C55, so you know it will work, though you will need to use Quartus, I think V16 or below, though you will need to check the supported versions.  I know Quartus V12 & programs chips fine in Win10.

You have enough IO for a 24bit DAC or HDMI transmitter (Look for a DDR interface 12 wire HDMI transmitter to still save IOs), enough more for a direct IO pin HDMI transmitter, and audio DAC and with 40k gates, you can make a hardware accelerated drawing engine, accelerated memory Flash card interface & add an 8 bit DDR2 ram chip.  (Careful here, you want the IO bank and it's voltage to be on one of the faster banks + on a separate voltage supply, but you can run it tops at 200MHz in DDR meaning 400Mb/sec.)

[BrianHG]

Also be careful of the larger Cyclone IV in the 144 pin package.  You loose some IOs since more IOs are changed into VCCint/core and GND pins as they are needed to power the larger core.

As for the CycloneIII, use an adjustable regulator for the core VCCint.  If you run the IC a little high at their max 1.25v, or 1.3v, you can push the C8 to run a single DDR2/3 ram chip to 500MHz without error.

[BrianHG]

I'm going to stick with Cyclone IV's for the moment as I have the dev environment set up for them - the above board will either use an EP4CE10 or CE15 FPGA, so the RAM will jump to 51 or 77KB respectively (and logic gate numbers increase respectively), but the package remains an easy-to-solder LQFP-144, minimising risk of problems/cost whilst I learn how to solder BGAs. 

Those memory figures are wrong.
Try 40 kilobytes for CE10 and 48 kilobytes for CE15.  Based on design, you can only sub-divide huge chunks of ram into dividends of 8 kilobytes, or smaller ones into 1/2/4/8 kilobytes.  You can test compile to check.  My suggested 240pin Cyclone III give you 120 kilobytes, + double the IOs + more than double the logic cells of the CE15.  With another 1 kilobyte for the palette, and another 1x2 kilobytes to cache the DDR memory.  Another 1x2 kilobytes to cache the flash ram card.  (This means a 320x240@256 color background with colored text and sprites with 15 MAGGIE layers before you even incorporate the 16 megabyte DDR2 ram chip)

Read the data sheet and learn what an M9K block is.  Also, since your memory allocation is using blocks divided into 16 bits instead of 18 bits, you loose some flexibility in memory allocation and you cannot use all the bits at your disposal.

[nockieboy]

For the future, the Lattice chip has 6x6 more pins than this chip Louis Rossmann is repairing in this video.
...
The secret here is the cleaning tinning of the pads and all that flux which helps transport the heat.
And a new PCB would be 100x cleaner than that water damaged mac.

He makes it look really easy actually - I guess with an SMT stencil and some decent flux, a BGA FPGA could be easier than an LQFP...

Do not got to the 30$ lattice chip, that one has it's solder balls at 0.5mm instead of 0.8mm.  But, if you do got that route and have your PCB manufacturer place the BGA for you, you will have 4megabits of graphics memory.

I'd have to be selling these things or crowd-funding the project if I was going to fund the cost for having a manufacturer place the BGA for me, it seems. 

You have enough IO for a 24bit DAC...

Yes, I'm just waiting on a DAC in the post to test my design on a PCB that will plug into the existing dev board and replace the 12-bit DAC.  I've built a 24-bit DAC into the new GPU board.

I'm going to stick with Cyclone IV's for the moment as I have the dev environment set up for them - the above board will either use an EP4CE10 or CE15 FPGA, so the RAM will jump to 51 or 77KB respectively (and logic gate numbers increase respectively), but the package remains an easy-to-solder LQFP-144, minimising risk of problems/cost whilst I learn how to solder BGAs. 

Those memory figures are wrong.
Try 40 kilobytes for CE10 and 48 kilobytes for CE15.  Based on design, you can only sub-divide huge chunks of ram into dividends of 8 kilobytes, or smaller ones into 1/2/4/8 kilobytes.  You can test compile to check.  My suggested 240pin Cyclone III give you 120 kilobytes, + double the IOs + more than double the logic cells of the CE15.  With another 1 kilobyte for the palette, and another 1x2 kilobytes to cache the DDR memory.  Another 1x2 kilobytes to cache the flash ram card.

Read the data sheet and learn what an M9K block is.  Also, since your memory allocation is using blocks divided into 16 bits instead of 18 bits, you loose some flexibility in memory allocation and you cannot use all the bits at your disposal.

I knew they were ball-park figures, but didn't realise I was that far out...    Will go look at the Cyclone III more closely - or may just have to jump straight to the Lattice then, taking the BGA leap in one go... I take it an FPGA wouldn't be hot-air solderable in BGA format, unlike the smaller chip in the video you linked?

[BrianHG]

I knew they were ball-park figures, but didn't realise I was that far out...    Will go look at the Cyclone III more closely - or may just have to jump straight to the Lattice then, taking the BGA leap in one go... I take it an FPGA wouldn't be hot-air solderable in BGA format, unlike the smaller chip in the video you linked?

In the video, the BGA was only 0.6mm smaller than the Lattice BGA.  What you saw was equivalent to a 100 pin BGA, 0.8mm.  The Lattice part is 256 pin.  (10x10 VS 16x16 balls)  Hot air with a ton of flux so the BGA floats when heated allowing it to self-center will solder easy.  The larger 4mb Lattice part with more IOs is actually a smaller IC since the ball pitch is 0.5mm.  That one I would leave to someone with superior gear to mount.

The Cyclone III is a normal QFP making life easy to solder and patch in an emergency where you can lift a pin.  You also get enough IOs to make 1 or 2 IO banks 2.5v for the DDR memory while leaving the other IO banks at 3.3v.  However, be warned, for the VCCint/core, make sure you have a 2 amp regulator since it can draw power if you fill up the IC completely with logic and max out the clock speed.  Same goes for the larger Cyclone IV chips.  This is why you loose IO pins on the larger Cyclone IV chips as those pins get changed into VCCint power pins to supply the core.

I would use the TI DVI transmitter listed earlier, and also add a second HDMI connector directly connected to IO pins to try out a soft serializer core which you may develop before going to a Lattice FPGA since you might be able to get rid of the TI DVI transmitter IC.

[nockieboy]

In the video, the BGA was only 0.6mm smaller than the Lattice BGA.  What you saw was equivalent to a 100 pin BGA, 0.8mm.  The Lattice part is 256 pin.  (10x10 VS 16x16 balls)  Hot air with a ton of flux so the BGA floats when heated allowing it to self-center will solder easy.

Fair enough - seems I don't even need to worry about a hot plate or reflow oven then?  That would make the setup a lot cheaper.

The Cyclone III is a normal QFP making life easy to solder and patch in an emergency where you can lift a pin.  You also get enough IOs to make 1 or 2 IO banks 2.5v for the DDR memory while leaving the other IO banks at 3.3v.  However, be warned, for the VCCint/core, make sure you have a 2 amp regulator since it can draw power if you fill up the IC completely with logic and max out the clock speed.  Same goes for the larger Cyclone IV chips.  This is why you loose IO pins on the larger Cyclone IV chips as those pins get changed into VCCint power pins to supply the core.

Those Cyclone IIIs sound better than the IVs...?  Which seems ironic due to their numbering...?

I would use the TI DVI transmitter listed earlier, and also add a second HDMI connector directly connected to IO pins to try out a soft serializer core which you may develop before going to a Lattice FPGA since you might be able to get rid of the TI DVI transmitter IC.

Okay, the TFP410?  Are there any reference designs floating around in the ether for that chip at all?  I'm Googling for ideas as I write this reply, but not finding any obvious tips.

As for the second HDMI connector - there's going to be preferential (high-speed IO) pins to connect it to on the FPGA, right?  I'm going to have to switch to the Cyclone III or Lattice FPGA for these as I don't have the spare IO on the Cyclone IV CE10 (no point using the CE15 really, as it's more expensive, still limited on RAM and less IO).

@jhpadjustable - don't know if you're still following this discussion, but if so, what considerations do I need to make regarding IO pins so that I can use the new 'v1' GPU card to develop audio output on it?  Would make absolute sense to include an audio driver of some description (or just reserve a couple of pins connected to a header) so that I at least have the option of developing the audio side in the FPGA.

[BrianHG]

Those Cyclone IIIs sound better than the IVs...?  Which seems ironic due to their numbering...?

Only the CycloneIV GX series offer a few different embedded hardware above the CycloneIII.  Otherwise, the III is identical to the IV which you are using in every respect, other than the 240pin QFP has been dropped for BGA packages only.

Read all you DVI transmitter datasheets... Also read the IO pins and their advanced uses in intel's manuals to know which IOs to use for ram & regular bus interface applications.  Read about audio DACs and how many IOs you need to operate them if you want sound.  TI has an absurd amount of info on audio DACs with different capabilities and prices.  Also, the DVI transmitters operate exactly like a video DAC, except you do not need to worry about driving the H&V sync down a video cable.  Also, the DVI transmitter can drive an HDMI connector as it is backwards compatible.  Also, the DVI transmitter may support multiplexed digital video meaning you send 12 bits, the upper 12 on a high clock, the lower 12 on a low clock meaning only 16 IOs in total are used instead of 28.

[BrianHG]

Hi @nockieboy, I hope you are progressing well.  Do you have schematics for us to look at and Gerbers yet?

I hope you purchased a few of those Cyclone IIIs.  As is usual here at EEVblog, when a good deal with a good project is listed, like a huge 100$ FPGA for 35$, in a hand solder-able QFP, the stock is now sold out.  You would need to purchase something like 1K pieces or an entire production run direct from Intel to get that price.

Do you have anything new to show us on the Z80 software driving the GPU?

Remember, the part number is 'EP3C40Q240C8N'

[nockieboy]

Hi @nockieboy, I hope you are progressing well.  Do you have schematics for us to look at and Gerbers yet?

Unfortunately, progress has been pretty slow as work is getting progressively busier as the month wears on.    Coincidentally, I have just finished an initial PCB design in the last couple of days though; schematics and PCB designs attached.  Would appreciate any feedback on them - especially if there's any problems or mistakes!  I'm not an electrical engineer and have no training, so I've tried my best to copy the schematic for the dev board where I can (rightly or wrongly) and add-in the bits and pieces I need.  I'm waiting on a couple of ADV7125s to arrive in the post so that I can test the 'video out' part of the circuit before committing the entire design to PCB.

I don't want bad design of the PCB to hinder later development of things like the keyboard interface, sound or SD card interface and what I've attached here is a first draft.  One thing I haven't done with the design is look at which signals go to which pins - a lot of what is connected where, and in which order, has been dictated by the board design and FPGA orientation to get a successful routing completed.  I need to review those connections and make sure it will work as intended.

I hope you purchased a few of those Cyclone IIIs.  As is usual here at EEVblog, when a good deal with a good project is listed, like a huge 100$ FPGA for 35$, in a hand solder-able QFP, the stock is now sold out.  You would need to purchase something like 1K pieces or an entire production run direct from Intel to get that price.

I haven't purchased any Cyclone III's just yet - my budget is restrictive at best (remember, I'm doing this purely as a hobby) and my confidence in building one of these PCBs and getting it right first time matches that, so I'm taking smaller, slower steps initially and designing for a Cyclone IV EP4CE10.  Once I'm happy that I've got the design considerations down for that and a working build (and can get rid of the dev board and mess of wires off my desk!), I'll either switch straight to a Lattice build if my design skills are up to the task and I'm feeling brave, or see about getting a Cyclone III. 

Parts are ordered for the first build - I haven't ordered the PCB yet (good thing as I hadn't thought you might want to check it out!) but they tend to get delivered a lot quicker than the parts do; seems that the parts come on the back of a tuk tuk or something from China.

Do you have anything new to show us on the Z80 software driving the GPU?

Other than the DMI monitor (some screenshots I've posted previously), there's nothing new really to show at the moment - I'm about to start working on the video driver for CP/M as soon as I get a day free to make a start on it, once that's done there'll be more to see. 

Quick question though - how did you get the Z80 image converted for the GPU?  Did you use stock software and something to save it in the required format, or write a converter yourself?  I'm using paint.net rather than Photoshop.

The other important thing I want to start testing shortly is the PS2 interface - need to get that up and running and sending chars to the Z80 via interrupts before I order the PCB, just so I'm happy the circuit will work.  With the FPGA using 3.3v, and needing to pull the 5v interrupt line low when required, I'm using a transistor to do that - hopefully that will work, but I've yet to set up a test.

[BrianHG]

Go for the cheapest version of the ADV7125 DAC, the 50MHz version, though the TI THS8136PHP is cheaper, faster and higher quality, but you need to run the IO and a bank on the FPGA at 1.8v, though, no voltage reference.
https://www.mouser.com/ProductDetail/Texas-Instruments/THS8136PHP?qs=sGAEpiMZZMswix2y39yldVRXhfgYHmM93ATDG4%252BVYYs%3D
vs
https://www.mouser.com/ProductDetail/Analog-Devices/ADV7125KSTZ50?qs=sGAEpiMZZMswix2y39yldfRSUiTQKynFVgceQfpCL2c%3D

Why are you clocking the DAC from your oscillator.  You should be using an output from the FPGA, preferably, one of the dedicated PLL output pins.  Use the second PLL CLK output if you have the reference oscillator on CLK1 input.

Why haven't you wired the 'blank' signal on the DAC to the video enable out.  It would help and also is necessary if you change the DAC for the DVI transmitter.

Things you can use the FPGA dedicated CLK inputs for:
clock oscillator <must be on a dedicated clock input for PLL to function  at high quality>
z80 clk input
Z80 buss controls, IE RD WR MREQ M1 INTA, IORQ, so long as all the buss controls are on the dedicated clock inputs.
reset
serial port RXD

I'm trusting you FPGA IO pins and part number.  Remember the EP4CE10E22C8N may have a few different IO pins than the EP4CE6E22C8N, typically a few less IOs changed into VCCint and GNDint.


What about the unused IOs on the SD-Card reader.

For the next revision, note that going straight to BGA means you cannot make a mistakes as you wont have access to pins to lift.

What size are your VIAs on your PCB.  are you sure any fab house can handle that in cheap PCB mode?  I know it's not a problem with higher quality expensive PCBs and if you are already using fine VIAs, you might as well go to a 4 layer PCB as it will be only a few dollars more from some China PCB manufacturers.

Are your power traces thin little traces like the data lines?


Your AMS1117-1.2 is ok for the EP4CE10E22C8N and you should expect it to get warm since it is linear with an almost 4v drop and a potential 0.25w VCCint load when switching your core to 15 layers.  This means around 208ma draw on a 800ma regulator.  With a 3.8v drop from the 5v supply = around 0.8 watts of dissipated waste heat.  (I'm assuming worst case with your current design).

Where is your 3.3v regulator?

You are going to get noise/ripples on you analog output with that ground layout and positioning of resistors.
Also, ADV7125 has an internal voltage reference mode.
With the ADV7125, also make sure the analog 5V is well filtered and isolated from the rest of your 5v design.

[nockieboy]

Go for the cheapest version of the ADV7125 DAC, the 50MHz version, though the TI THS8136PHP is cheaper, faster and higher quality, but you need to run the IO and a bank on the FPGA at 1.8v, though, no voltage reference.

Yes, I've gone for the 50 MHz version.

Why are you clocking the DAC from your oscillator.  You should be using an output from the FPGA, preferably, one of the dedicated PLL output pins.  Use the second PLL CLK output if you have the reference oscillator on CLK1 input.

Erm...    I guess because it's a 50 MHz clock and the DAC is 50 MHz, it seemed like a good idea at the time?  I take it using CLK7, 6, or 4 wouldn't be an issue?  It would make routing easier?

Why haven't you wired the 'blank' signal on the DAC to the video enable out.  It would help and also is necessary if you change the DAC for the DVI transmitter.

No particular reason, other than I guess I thought it wasn't needed.  Have added it in then. 

Things you can use the FPGA dedicated CLK inputs for:
clock oscillator <must be on a dedicated clock input for PLL to function  at high quality>
z80 clk input
Z80 buss controls, IE RD WR MREQ M1 INTA, IORQ, so long as all the buss controls are on the dedicated clock inputs.
reset
serial port RXD

I'm trusting you FPGA IO pins and part number.  Remember the EP4CE10E22C8N may have a few different IO pins than the EP4CE6E22C8N, typically a few less IOs changed into VCCint and GNDint.

Well, I've yet to go through and confirm that the pins are all okay.  The realisation that the reference design I've been working from is for the CE6 version has caused me to go dig up a reference for a CE10 version - I'll go through the pins when I get a chance.

What about the unused IOs on the SD-Card reader.

Well, I was getting short of IOs so it seemed a 1-bit connection was the best idea - again, based off of example schematics I'd found elsewhere...

What size are your VIAs on your PCB.  are you sure any fab house can handle that in cheap PCB mode?  I know it's not a problem with higher quality expensive PCBs and if you are already using fine VIAs, you might as well go to a 4 layer PCB as it will be only a few dollars more from some China PCB manufacturers.

Ah, well spotted.  They're 10mil vias (20mil overall) - I've just checked with JLCPCB and it appears I can go that small on a multi-layer PCB, but not on a 2-layer PCB. 

Are your power traces thin little traces like the data lines?

Most traces are 8mil, or 12mil for the 5v lines, with 6mil minimum spacing for all?  I guess with the power requirements of the EP4CE10, I'll need wider traces on ALL the power lines?

Where is your 3.3v regulator?

That's off-board, on another card in the stack along with the 5v regulator.  I guess I could do with adding a cap or two to that supply as it comes onto the card.

You are going to get noise/ripples on you analog output with that ground layout and positioning of resistors.
Also, ADV7125 has an internal voltage reference mode.
With the ADV7125, also make sure the analog 5V is well filtered and isolated from the rest of your 5v design.

I'm into new territory here. How do I need to improve the ground layout?  Are there any guides or tutorials on this sort of thing?  So I don't need the AD1580 voltage reference?  I'll go see what I can learn about power supply filtering and isolation.. 

[BrianHG]

Go for the cheapest version of the ADV7125 DAC, the 50MHz version, though the TI THS8136PHP is cheaper, faster and higher quality, but you need to run the IO and a bank on the FPGA at 1.8v, though, no voltage reference.

Yes, I've gone for the 50 MHz version.

Why are you clocking the DAC from your oscillator.  You should be using an output from the FPGA, preferably, one of the dedicated PLL output pins.  Use the second PLL CLK output if you have the reference oscillator on CLK1 input.

Erm...    I guess because it's a 50 MHz clock and the DAC is 50 MHz, it seemed like a good idea at the time?  I take it using CLK7, 6, or 4 wouldn't be an issue?  It would make routing easier?

The dac CLK needs to be the pixel clk, not the 50MHz clk.
You cannot use the FPGA dedicated CLK inputs as an output to drive the DAC clk input.  They are inputs only.  Read the Intel datasheet and find out which output are connected to a PLL clock output.

Why haven't you wired the 'blank' signal on the DAC to the video enable out.  It would help and also is necessary if you change the DAC for the DVI transmitter.

No particular reason, other than I guess I thought it wasn't needed.  Have added it in then. 

Things you can use the FPGA dedicated CLK inputs for:
clock oscillator <must be on a dedicated clock input for PLL to function  at high quality>
z80 clk input
Z80 buss controls, IE RD WR MREQ M1 INTA, IORQ, so long as all the buss controls are on the dedicated clock inputs.
reset
serial port RXD

I'm trusting you FPGA IO pins and part number.  Remember the EP4CE10E22C8N may have a few different IO pins than the EP4CE6E22C8N, typically a few less IOs changed into VCCint and GNDint.

Well, I've yet to go through and confirm that the pins are all okay.  The realisation that the reference design I've been working from is for the CE6 version has caused me to go dig up a reference for a CE10 version - I'll go through the pins when I get a chance.

What about the unused IOs on the SD-Card reader.

Well, I was getting short of IOs so it seemed a 1-bit connection was the best idea - again, based off of example schematics I'd found elsewhere...

What size are your VIAs on your PCB.  are you sure any fab house can handle that in cheap PCB mode?  I know it's not a problem with higher quality expensive PCBs and if you are already using fine VIAs, you might as well go to a 4 layer PCB as it will be only a few dollars more from some China PCB manufacturers.

Ah, well spotted.  They're 10mil vias (20mil overall) - I've just checked with JLCPCB and it appears I can go that small on a multi-layer PCB, but not on a 2-layer PCB. 

Are your power traces thin little traces like the data lines?

Most traces are 8mil, or 12mil for the 5v lines, with 6mil minimum spacing for all?  I guess with the power requirements of the EP4CE10, I'll need wider traces on ALL the power lines?

You should only use the 6 mil spacing between traces-traces and pads.  You should have something like 10 or 12 mil spacing for everything else like polygon fills.
5V and 3.3V & 1.2v, if not filled should be at least 50mil for the most part.  Make sure you have no weak points and don't pass through single vias, or any at all.

Where is your 3.3v regulator?

That's off-board, on another card in the stack along with the 5v regulator.  I guess I could do with adding a cap or two to that supply as it comes onto the card.

You are going to get noise/ripples on you analog output with that ground layout and positioning of resistors.
Also, ADV7125 has an internal voltage reference mode.
With the ADV7125, also make sure the analog 5V is well filtered and isolated from the rest of your 5v design.

I'm into new territory here. How do I need to improve the ground layout?  Are there any guides or tutorials on this sort of thing?  So I don't need the AD1580 voltage reference?  I'll go see what I can learn about power supply filtering and isolation.. 

Your ground around the VGA connector and dac and 75 ohm load resistors is broken up and not solid.  It routs as a large open object which connects at some different GND points at the outer edges.  Also, your 5v feeding the DAC is your digital 5v.  You need an analog 5v.  A separate 5v from it's own dedicated 5v regulator whose GND is referenced right at the DAC's analog GND and VGA connector's GND return pins for the R&G&B wires.  Make sure you feed the DAC's 5v regulator with 9v to 12v through a series RC or RLC filter whose filter termination attaches to the DAC's analog GND.

Read the dac data sheet, it tells you how to operate the DAC using it's internal voltage reference.

[nockieboy]

You should only use the 6 mil spacing between traces-traces and pads.  You should have something like 10 or 12 mil spacing for everything else like polygon fills.
5V and 3.3V & 1.2v, if not filled should be at least 50mil for the most part.  Make sure you have no weak points and don't pass through single vias, or any at all.

Righto, will sort that on the next revision. Vias are unavoidable on a 2-layer board.  Might have a look at what the cost of a 4-layer board would be.

If I'm going multi-layer, it'll be for the first time ever.  Are there any particular considerations I need to bare in mind? Should I separate the power and ground planes with the signal plane (or not), for example?

Also, ADV7125 has an internal voltage reference mode.
With the ADV7125, also make sure the analog 5V is well filtered and isolated from the rest of your 5v design.

Your ground around the VGA connector and dac and 75 ohm load resistors is broken up and not solid.  It routs as a large open object which connects at some different GND points at the outer edges.  Also, your 5v feeding the DAC is your digital 5v.  You need an analog 5v.  A separate 5v from it's own dedicated 5v regulator whose GND is referenced right at the DAC's analog GND and VGA connector's GND return pins for the R&G&B wires.  Make sure you feed the DAC's 5v regulator with 9v to 12v through a series RC or RLC filter whose filter termination attaches to the DAC's analog GND.

Read the dac data sheet, it tells you how to operate the DAC using it's internal voltage reference.

I'm a little confused by the data sheet, to be honest.  It states there's an internal reference mode, but then states that the Vref pin should be connected up as per the application schematic (figure 12, page 15 of the datasheet), where it shows an external reference being used and makes no mention of how to enable the internal reference mode.  All I can surmise is that the diode and resistor should be removed and a capacitor (value unknown) placed in series with Vaa feeding the Vref pin?

Also, the 5V supply is direct from the USB port in this instance.  Or it could be from a 5V regulator if a 9-18V power supply is used.  Creating an analogue 5V supply is not going to be easy and will require modifications and a new version to an existing card that handles the power supply for the computer.

[BrianHG]

Also, the 5V supply is direct from the USB port in this instance.  Or it could be from a 5V regulator if a 9-18V power supply is used.  Creating an analogue 5V supply is not going to be easy and will require modifications and a new version to an existing card that handles the power supply for the computer.

USB5v powering an analog 5v device...
Give me some time to think of something.

[BrianHG]

You should only use the 6 mil spacing between traces-traces and pads.  You should have something like 10 or 12 mil spacing for everything else like polygon fills.
5V and 3.3V & 1.2v, if not filled should be at least 50mil for the most part.  Make sure you have no weak points and don't pass through single vias, or any at all.

Righto, will sort that on the next revision. Vias are unavoidable on a 2-layer board.  Might have a look at what the cost of a 4-layer board would be.

If I'm going multi-layer, it'll be for the first time ever.  Are there any particular considerations I need to bare in mind? Should I separate the power and ground planes with the signal plane (or not), for example?

Your going to need to make the bottom almost all GND and thick VCC/VCCint/VCCa.  You will need multiple parallel vias for the power traces.  Coming from the regulators, use 50mil, but you may shrink them to 20 mils approaching the FPGA and other ICs, as long as the decoupling caps are next to a large filled GND plane.  Don't bother filling the top with a GND plane, it will just make you be sloppy about placing the GND and this allows you to focus on layout and IO pin selection.

You may take a few liberties with the 245 buffers, but with your layout, you probably wont need to.

Your design is simple enough to go with 2 layer, just need to do things a little smarter.

[nockieboy]

Also, the 5V supply is direct from the USB port in this instance.  Or it could be from a 5V regulator if a 9-18V power supply is used.  Creating an analogue 5V supply is not going to be easy and will require modifications and a new version to an existing card that handles the power supply for the computer.

USB5v powering an analog 5v device...
Give me some time to think of something.

Let me add that the USB power supply is NOT a permanent thing.  All this time the Microcom has been slaved to a host PC so I can see its output and talk to it via a serial console.  With the addition of a video card and PS2 keyboard, it won't need to be connected to a host computer any more and so its usual method of receiving power will be via a 12V source (wall wart?).

[BrianHG]

Also, the 5V supply is direct from the USB port in this instance.  Or it could be from a 5V regulator if a 9-18V power supply is used.  Creating an analogue 5V supply is not going to be easy and will require modifications and a new version to an existing card that handles the power supply for the computer.

USB5v powering an analog 5v device...
Give me some time to think of something.

Let me add that the USB power supply is NOT a permanent thing.  All this time the Microcom has been slaved to a host PC so I can see its output and talk to it via a serial console.  With the addition of a video card and PS2 keyboard, it won't need to be connected to a host computer any more and so its usual method of receiving power will be via a 12V source (wall wart?).

I read the ADV7125 data sheet, it specifically says the dac can operate with a Vaa at 3.3v on page 4 of 17.  Use a dedicated 3.3v 150-350ma regulator powered from 5v with the input filter I mentioned.  This will allow you to filter your 5v supply to a clean 3.3v for the analog video out.

For the v-ref, as an output, just place the cap, no resistor.  But, I would place dummy pads for the resistor and reference diode since you may just leave them unpopulated.

Here is the cheapest ADV7125:
https://www.chip1stop.com/view/dispDetail/DispDetail?lang=en&cont=USA&partId=AD01-0052199&mpn=ADV7125KSTZ50&keyword=adv7125

[nockieboy]

I read the ADV7125 data sheet, it specifically says the dac can operate with a Vaa at 3.3v on page 4 of 17.  Use a dedicated 3.3v 150-350ma regulator powered from 5v with the input filter I mentioned.  This will allow you to filter your 5v supply to a clean 3.3v for the analog video out.

For the v-ref, as an output, just place the cap, no resistor.  But, I would place dummy pads for the resistor and reference diode since you may just leave them unpopulated.

  Sounds like a plan.

Here is the cheapest ADV7125:
https://www.chip1stop.com/view/dispDetail/DispDetail?lang=en&cont=USA&partId=AD01-0052199&mpn=ADV7125KSTZ50&keyword=adv7125

I ordered mine here: https://www.aliexpress.com/item/4000433708668.html?spm=a2g0s.9042311.0.0.27424c4dqtzxLQ

..but I notice it's a 240MHz part.  Should be okay though running at 50 MHz? 

[BrianHG]

..but I notice it's a 240MHz part.  Should be okay though running at 50 MHz? 

? Your pixel clock is 25MHz, not 50.  Your need to clock the DAC at 25MHz to match your pixel clock speed.  The 240 is the upper limit.
Also, those at Aliexpress, what does the chip look like.  Though they might be fake, or 50Mhz relabeled at 250, they are a simple enough component which should still work fine.

[nockieboy]

? Your pixel clock is 25MHz, not 50.  Your need to clock the DAC at 25MHz to match your pixel clock speed.

Yep, you got me.  I should stop trying to do two things at once. 

The 240 is the upper limit.
Also, those at Aliexpress, what does the chip look like.  Though they might be fake, or 50Mhz relabeled at 250, they are a simple enough component which should still work fine.

That's okay then.  Yes, it's always a concern about getting fake components, my luck will run out at some point... 

[BrianHG]

Ok, here are the actual limits of each intel FPGA as I compiled your project with these chips:

Code: [Select]

-----------------------------------
EP4CE6E22C8
NUM_LAYERS = 7
ADDR_SIZE = 15
NUM_WORDS = 24576

Logic cells = 95% full
Remaining 1kbyte blocks = 5.
-----------------------------------
EP4CE10E22C8
NUM_LAYERS = 13
ADDR_SIZE = 16
NUM_WORDS = 40960

Logic cells = 96% full
Remaining 1kbyte blocks = 5.
-----------------------------------
EP4CE15E22C8
NUM_LAYERS = 15
ADDR_SIZE = 16
NUM_WORDS = 53248

Logic cells = 75% full
Remaining 1kbyte blocks = 3.
-----------------------------------
EP4CE40F23C8N OR EP3C40Q240C8N
NUM_LAYERS = 15
ADDR_SIZE = 17
NUM_WORDS = 122880

Logic cells = 30% full
Remaining 1kbyte blocks = 5.
-----------------------------------
Num_words is the bytes of available GPU display ram, + another 1024 for the palette.
Num_layers is the available display windows/sprites.  By now, you know what that means...

I was wrong about the 'EP4CE15E22C8', you actually make it to 53.248kb instead of 48kb.
The cyclone III makes it to 122.88kb + space and IO pins for a 128mb or 1gb DDR2 Dram + another 3 MAGGIE layers for the Dram's contents (18 total MAGGIEs), but, your Z80 has so little address space that the 1gb may be too much.

Since you are using the slowest -C8 versions, and, you need a C7, or even a -C6 for the higher densities, I recommend replacing the 1.2v regulator for an adjustable one and adjust it for 1.35v.  This will make a C8 perform somewhere inbetween a C7 and C6 which would be perfect.  Though, my GPU design, there are only a few critical address paths in the FPGA, so it still wont get warm or draw too much current over driving the VCCint to 1.35v.

[BrianHG]

Wow, Aliexpress has this EP4CE55F23C8N:
https://www.aliexpress.com/item/4000565235137.html?spm=a2g0o.productlist.0.0.6f4070d8TJDFSw&algo_pvid=32026952-2ec8-4c29-8482-f604669bd0df&algo_expid=32026952-2ec8-4c29-8482-f604669bd0df-10&btsid=81dd9ffb-1486-42b3-a4ca-3047c798def0&ws_ab_test=searchweb0_0,searchweb201602_7,searchweb201603_55

At 2.3 megabit, that's slightly larger than the 1.9 megabit Lattice part.  Though, the 16$ lattice part is coming from reputable sources like Digikey and Mouser and you are guaranteed a legitimate part.  Digikey lists the EP4CE55F23C8N at $115 usd, so that 18$ Aliexpress price sounds too fishy.