Hi all,
I have this strange problem that I haven't seen on the net.
I'm configuring a DMA in a block design for the Zynq and disabling SG mode as it's simple not needed for this part of the design. Please see the screenshot of the configuration below.
However even after reseting the block design outputs, reseting the synth, generating the bitstream and exporting the HW I still get SG mode enabled in the xparameters header file!? So when I try to use the simple mode it errors out saying it's incompatible with SG.
In Vitis I reimport the hardware, clean and build. A loop I've been running for a weeks now without an issue like this.
Any thoughts would be amazing!
Thanks