Termination can be selected via soft control on most modern FPGAs. Read up on your FPGA's advanced IO buffer primitive. Note that this is advanced and you will need to use a different custom primitive for every FPGA vendor and every different FPGA series that vendor sells.
Voltage cannot be adjusted as it is a function of wiring the VCCIO pin for that IO bank.
Unless you are running at the high megabit/gigabit, using one IO voltage for both 3.3v/2.5v with a software adjustable termination sequence, you can achieve functionality as long as you don't exceed the input max voltage compared to VCCIO wiring and use a true differential input instead of a emulated differential input. However, expect diminished peak performance with regard to bitrate, noise, and precision timing alignment.