Efinix

[SiliconWizard]

https://www.efinixinc.com/products.html

Has anyone heard of them?

[ebclr]

1st time, appear interesting

[mark03]

The Efinix® Trion® programmable platform, built on Efinix Quantum™ technology, delivers substantial Power-Performance-Area advantages over traditional FPGA products. Trion FPGAs feature programmable logic and a routing fabric built using Quantum technology.

Fairly useless marketing-ese.  Anyone care to speculate what their "Quantum technology" actually is?  And what gives this an edge over "traditional" FPGA products?

Their initial package matrix is pretty awful.  Nothing in a low-ball-count package except for the tiniest devices, and only enormous-ball-count packages for their larger devices.  It is even more extreme than, e.g., Xilinx:  fully half of the line is only available in packages with more than 256 balls!  And of course no QFN options, which is perhaps more understandable, but still unfortunate.  I don't understand why no one caters to applications which need lots of fabric but very little I/O?

[mark03]

So they actually do say more on their technology page:

The basic building block of the Quantum technology is the eXchangeable Logic and Routing (XLR) cell. An XLR cell can function as either a LUT-based logic cell or a routing switch encoded with a scalable, flexible routing structure. This innovation improves the active area utilization by 4X compared to traditional FPGAs, resulting in up to 4X area efficiency and a 2X power advantage. The power, performance, and area advantage is scalable by logic density.

This doesn't sound like it involves any new process technology, just a design innovation.  After decades of progress in programmable logic, how is it that Efinix have come up with this [apparently revolutionary] advance while Xilinx/Intel are stuck with inefficient legacy designs? But what do I know...?  Curious what the seasoned FPGA folks think.

[ebclr]

I guess Risc V is the thing

[jhpadjustable]

This doesn't sound like it involves any new process technology, just a design innovation.

There was a time when "innovation" meant "false prophecy", and in subtext it remains so today. If it were really "quantum" each cell could act as both logic and routing at the same time.  Oh well, any load of to create patentable subject matter to keep the game going.

Another Chinese FPGA startup moved to the people's republic of California. Don't know what toolchain they are using and don't know much about their products.
Maybe someone can test the water?

They're apparently a joint venture including Xilinx. I think Efinix are in it to get bought. Moving back to the USA is a natural move under such circumstances.

[SiliconWizard]

Another Chinese FPGA startup moved to the people's republic of California. Don't know what toolchain they are using and don't know much about their products.
Maybe someone can test the water?

Yeah, I'd be curious to do that, just to see. Unfortunately, you need to buy at least a dev kit to be able to download the tools. I'll see.

[djnz]

Somewhat cheaper dev board:
https://www.crowdsupply.com/xips-technology/fireant

Software (~ 260MB in size), link should be valid till about Christmas 2019:

Windows 64 bit:
https://transfer.sh/102PQ2/efinity-windows-x64.msi

Ubuntu linux 64 bit:
https://transfer.sh/12FHcs/efinity-ubuntu-x64.tar.bz2


I haven't had time to play with it much but like that the software seems quite light-weight. I am very interested in hearing the views of more experienced forum veterans about the software.

[Smokey]

Resurrecting this old thread because they are the only parts readily in stock at Digikey right now. 

I found this article from 2019: https://www.eejournal.com/article/efinix-yet-another-fpga-company/

Anyone used their FPGAs in an actual design?

[asmi]

I wanted to give it a try, but their IDE is not available publicly (you have to buy a devkit to get access to it), which is a problem if I would want to design a more sensible devboard and somebody else would want to use it, and their own devboards are insanely overpriced for what they are. It's almost as if they are trying to hide a license cost of IDE in prices of their devkits. NOT a good idea.

[mon2]

Hi. Have worked with the Ti60 since the introduction. Faced assorted hurdles including 3 weeks of trying to convince the factory that their demo examples and documentation were flawed. After some brow beating, they agreed and have since then, corrected the bugs we reported.

We are in a similar boat with GOWIN -> now the factory is silent. Had excellent support from Gowin till we alerted the HYPER RAM IP was buggy. Crickets after this reporting.

I get it, 'buy containers of our devices and without support'. Wish we could do the same. Our building is full of buggy silicon so no thank you. We will buy when we are confident the devices function as advertised.

We are still very green (not meaning low power) to FPGA devices but apparently can locate bugs that the factory could not.

The tech support from Efinix has been excellent and David (FAE; USA) from Gowin has been amazing till the last bug reporting.

The IDE from Efinix does not expire but a valid kit is required for the updates. Noting these conditions, I am confident they will not have an issue to share the IDE here. Have had these open chats with Roger (Efinix, USA) in the past.

Is that of interest ? Can share via  a cloud account. We have a few years of active account support with Efinix.

Would not hesitate to work with either company if you are comfortable with their toolchain / IP generation. We have active designs in development with both vendors.

Wish to comment that the GOWIN toolchain is quite fast from start to end - can generate a binary image in a few minutes or sooner (sometimes seconds).

The Efinix toolchain takes about 35-40 mins on average to almost 1 hour. Just a FYI.

[up8051]

Had excellent support from Gowin till we alerted the HYPER RAM IP was buggy.

Does this also apply to PSRAM Controller IP?
Can you say more about this bugs?
Just started trying with PSRAM Video Buffer (GW1NR-9).

[mon2]

Please see here:

https://www.reddit.com/r/FPGA/comments/vdzowh/using_gowin_gw1nsrlv4c_psram_and_hyperram/

I posted the details there. Still have not resolved the fault but it is enough, for now, to use this external storage for data / FIFOs / serial port buffering. In the near future, need  this working properly for video bitmap storage for MIPI DSI projects.

[asmi]

The IDE from Efinix does not expire but a valid kit is required for the updates. Noting these conditions, I am confident they will not have an issue to share the IDE here.

If so they would've just posted a download link publicly/behind free ITAR check, like every other FPGA vendor is doing. I'm really interested to play around with their software, but I don't feel like dumping $500+ for their devboard just to satisfy my curiousity. Parts by themselves look somewhat interesting, due to the 16 nm process the fabric should be quite fast.

[mon2]

You can receive full access to their toolchain / IP for a year with one of their lower cost kits through Digikey:
   
p/n: 2134-XYLONI-ND

Xyloni FPGA T8F81 Trion® FPGA Evaluation Board

https://www.digikey.ca/en/products/detail/efinix-inc/XYLONI/13535080

This used to be a $35 USD kit (pre-covid).

[asmi]

You can receive full access to their toolchain / IP for a year with one of their lower cost kits through Digikey:
   
p/n: 2134-XYLONI-ND

Xyloni FPGA T8F81 Trion® FPGA Evaluation Board

https://www.digikey.ca/en/products/detail/efinix-inc/XYLONI/13535080

This used to be a $35 USD kit (pre-covid).

$110 for a useless devboard which will be collecting dust? No thank you.

[AndyC_772]

I'm busy porting a design to Efinix right now, thanks to the complete failure of Intel to make Cyclone parts available any longer.

So far, my impressions are:

- I can actually buy them. Can't overstate just how important this is. Seriously, it trumps absolutely everything else.

- Having to buy a Xyloni board to get a licence key was a completely trivial non-issue. I'm using these products commercially, so a 2 or low 3 figure sum to obtain the dev tools doesn't even warrant the time spent to think about it. The value of my time that'll be spent porting the design, not to mention the commercial value of the end product, makes it barely even a rounding error. Just order the board.

- Support from the manufacturer has been good so far. Yes, you read that correctly - support from the actual manufacturer. Try getting that from one of the bigger players.

- There are some important architectural quirks, especially to do with the internal interface between the programmable core and the completely logically separate I/O ring (which includes PLLs, DDIO interfaces and optional latches). It's like having two physically separate parts inside the same package, and I've yet to find anything I actually like about that.

- Timing constraints are applied to the core, NOT the physical pins of the device. If anyone's figured out how to apply constraints that govern, say, the Tco for a data pin on the FPGA relative to a clock pin also driven by the FPGA, then do please let me know. This does seem to be an area in which that separation between core and I/O ring is particularly awkward.

- Documentation surrounding timing constraints is - as per the industry standard - incredibly unclear. Would it really be asking too much to be told 'this is the delay from specific point A to specific point B when triggered by specific clock C' - complete with a few diagrams and worked examples?

- On the subject of timing - the synthesis tool appears incapable of inserting delays to cope with internal clock skew. So, for example, you can create a slow clock from a fast one by using a logical counter, but you'll struggle to pass data between those two clock domains because the tool can't then meet hold timing when going from the slower domain to the faster one. This is a big difference, and a major limitation, compared to Altera / Quartus, which copes admirably with this scenario.

[asmi]

- I can actually buy them. Can't overstate just how important this is. Seriously, it trumps absolutely everything else.

Yes, that is a big reason I'm considering looking at them as well.

- Having to buy a Xyloni board to get a licence key was a completely trivial non-issue. I'm using these products commercially, so a 2 or low 3 figure sum to obtain the dev tools doesn't even warrant the time spent to think about it. The value of my time that'll be spent porting the design, not to mention the commercial value of the end product, makes it barely even a rounding error. Just order the board.

It's a point of principle. I don't know how it works with Antel, but with Xilinx once you buy a license, that version stays with you FOREVER without a need to buy any upgrades. You only renew license if you want to get access to newer versions of software. But for many parts they just provide a free version which can be freely downloaded (without buying any of their devboards) and used forever without any time limitations.

- Support from the manufacturer has been good so far. Yes, you read that correctly - support from the actual manufacturer. Try getting that from one of the bigger players.

This is balanced by the fact that you don't require support from big mfgs nearly as often. Also from my personal experience, on a few times I actually needed their support, I was able to get it in a timely fashion. So not really an advantage here.

- On the subject of timing - the synthesis tool appears incapable of inserting delays to cope with internal clock skew. So, for example, you can create a slow clock from a fast one by using a logical counter, but you'll struggle to pass data between those two clock domains because the tool can't then meet hold timing when going from the slower domain to the faster one. This is a big difference, and a major limitation, compared to Altera / Quartus, which copes admirably with this scenario.

Unfortunately timing is a PITA in pretty much all toolchains, and poor documentation doesn't really make things easier. But using logic to create clocks is incredibly bad idea anyways (that's what PLLs are for!), so no big problem here.

One more major point is their IDE doesn't seem to come with any simulator. That is a BIG problem for me.

[Neilm]

I'm busy porting a design to Efinix right now, thanks to the complete failure of Intel to make Cyclone parts available any longer.

I am in the same boat for the same reasons. I think Intel are going to make that obsolete - we have been quoted 2024 for parts.

The toolset seems to be a bit immature and the split between the logic and the IO doesn't make sense. So far, the bits that annoy me the most are that some of the IP cores are generating warnings (seriously) and a bidirectional port is fiddly to use. You have to generate an input, an output and an enable line then mash them together. Very annoying if the signal is going a few blocks deep. Also, the tool set does not seem to want to use logic to generate multipliers. I'm not going to moan about the FIR IP as it is a prototype they note is not finished (but if they implementd a folding parrallel FIR it would fit the chip I originally speced)

I am just starting to look at fixing the timing issues so... Yay

[SpacedCowboy]

It's a point of principle. I don't know how it works with Antel, but with Xilinx once you buy a license, that version stays with you FOREVER without a need to buy any upgrades. You only renew license if you want to get access to newer versions of software. But for many parts they just provide a free version which can be freely downloaded (without buying any of their devboards) and used forever without any time limitations.

That's the sort of thing that a bigger company can afford. Smaller guys need revenue streams and even nominal ones add up over time.

FWIW, when my license ran out, I just pinged support and they gave me an extra year, no questions asked. I'll echo the comment below that the support is excellent.

- Support from the manufacturer has been good so far. Yes, you read that correctly - support from the actual manufacturer. Try getting that from one of the bigger players.

This is balanced by the fact that you don't require support from big mfgs nearly as often. Also from my personal experience, on a few times I actually needed their support, I was able to get it in a timely fashion. So not really an advantage here.

You must have much better contacts at Xilinx and Altera than I do then. When I had an issue with the SDRAM controller, we exchanged emails even late at night (and Rochelle was based in the same timezone as I am in), and even on weekends. When that didn't fix it, she set up a video conference so we could walk it through together.

I've never had anything even remotely like that from the big players, and Efinix know I'm small-fry - they know they probably won't get huge business from me, so it's even more impressive IMHO. Of course, I do tend to tell people about how good their support is at every opportunity - so maybe it's paying off for them that way [grin].

One more major point is their IDE doesn't seem to come with any simulator. That is a BIG problem for me.

Yep, this is a downside. I was using Icarus / GTKwave.

[AndyC_772]

some of the IP cores are generating warnings (seriously)

Yep - today I spotted that the dual clock FIFO is complaining about an internal reset signal not being connected.

I've also just found out that the same function's 'empty' output doesn't seem to work at all - maybe it's synchronised to the read clock, which in my design, doesn't run until there's something in the buffer to read.

Chicken, egg, and all that. Maybe it's something to look at on Monday.

I am just starting to look at fixing the timing issues so... Yay

Good luck!

[Neilm]

some of the IP cores are generating warnings (seriously)

Yep - today I spotted that the dual clock FIFO is complaining about an internal reset signal not being connected.

That is one of them I have found - along with size mismatches getting truncated.

I am just starting to look at fixing the timing issues so... Yay

Good luck!

Thanks - I have a horrible feeling I'll need it...

Neil

[glenenglish]

I've a heavy Xilinx user. Well, small SPartan7 up to MPSoC Ultrascale+ (which I love and hate due to the 12,000 pages of doco you really DO need to read)....

I have been evaluating the Efinix parts the past 4 months. I bought a Xyloni kit to start(never used). and now I have a Ti180-M484 Dev kit to show them I am at least half serious.

The manufacturer's factory and representative support (Braemac) has been excellent.

I get the feeling the devices are good, but the toolchain is young.

I rely quite heavily on alot of the xilinx IP. to move some of those designs to efinix I will need to do things a different way- which means writing my own cores (likely wit the bare minimum of paramaterization) with  high level synthesis , which the mfr support have been good with guidance- of course this technique usually chews logic cells like there is no tomorrow, so I think the 180 size part will be suitable to replace the a 50k logic cell heavily optimized with xilinx core xilinx.....  They are FAST ! Sure I can use that multiplier 4x as fast. but- it takes work to use that speed. IE sharing DSPs to do different jobs, multiple jobs etc is non trivial.

the leakage is very low. price is good.  very good, but I have a bunch of IP to write. and its verilog centric. groan, (I am a VHDL shop)

My work is 99% signal processing with screaming DDR converter interfaces.  (SDR platforms)
-glen

[glenenglish]

NEIL- xilinx cores do that also. that is pretty normal stuff. expect loads of warnings from cores.
-glen

some of the IP cores are generating warnings (seriously)

Yep - today I spotted that the dual clock FIFO is complaining about an internal reset signal not being connected.

[asmi]

For me the lack of built-in simulator is a big problem. I'm too used to Xilinx full-featured sim being always available, and, more importantly, I can be sure that what it outputs is what's actually going to happen in a real life - including timing-wise. Also I've been using AXI Verification IP for pretty much all of my component designs that use AXI bus in some way or another as it not only ensures compliance, but also provides great sim capabilities like easy generation of AXI requests, and simulating AXI memories for sim/debug purposes.