clocking scheme/CDC for half-band filter

[jlcordar]

I've done some FPGA design but not any multi-bit multirate stuff.  I designed a half-band filter in SystemVerilog, and I will decimate the filter output by 2.  The decimated clock is derived from the clock the filter is running at (implemented a /2 since the speed was too low for the FPGA PLL to generate the clock). 

To handle the different clock domains, should I do Multi-Cycle Path or a short rate adaptation async FIFO or something else? 
This will be in Efinity because I can't find any other cheap boards at the moment. 

For a CIC filter, I imagine it would be the same answer just with a greater clock difference between the clocks.  This is for PDM -> I2S. 

thanks.

[Someone]

Where there are integer ratio clocks (particularly 2^n ratios, but the concept still works even for non integers) it is more common to leave everything on the "fast" clock and use clock enables for the parts that operate slower.

[jlcordar]

thanks, I'll try to implement w/clock enables.  I'll try the async FIFOs later but I'll try clock enables first.