I'm playing around with Vivado and adding stuff to the PL. I notice in the original devicetree there are just two IP instances in the PL, one is a BRAM controller, the other one is a Uartlite core. However, I don't see in the schematic any external connection for the Uartlite. Does anyone have a clue? I thought I could just use on of the fan control sockets, but unfortunately they are connected only to PS pins, not to PL pins.
I made a big step forward and fell into a hellhole. The big step was building my own linux kernel and devicetree and running it on the board. The hellhole was completely trashing the NAND flash with careless use of "nand write"
I'm now clawing my way back up, but it involves doing things that I'd rather have avoided. Among these are:
- using "Vitis" to create a FSBL that disregards the bootmode resistors and boots straight into JTAG mode
- compiling a working u-boot for the board
- loading the FSBL into on-chip memory via JTAG
- actually modifying the JTAG (extending the CPLD buffer of a DP Busblaster V4) to have a UART on the second FTDI channel (this involves installing an ancient version of the Xilinx ISE toolchain to reprogram a Coolrunnner II CPLD and some VHDL hacking)
- loading u-boot into DDR via JTAG and debugging it with gdb to find out why it doesn't start
- finally getting u-boot to run, using the UART channel of the JTAG to talk to it
- creating a working fsbl-uboot binary, uploading it via serial (y-modem) and flashing it into NAND <-- I AM HERE
Obviously, I had a lot of fun