EBAZ4205 (Zynq-7000 based development board)

[thinkfat]

point vs. comma    ?

with a 33.333333MHz input I get 30x for the IO pll = 1000MHz, and a /8 /5 to get a 25.0000MHz PL clock

Yup, that was the reason in the end. Launching Vivado with an all-English locale did the trick. I had LC_NUMERIC set to "de_DE.UTF-8" and that made it disregard the decimal point.

[thinkfat]

point vs. comma    ?

with a 33.333333MHz input I get 30x for the IO pll = 1000MHz, and a /8 /5 to get a 25.0000MHz PL clock

Yup, that was the reason in the end. Launching Vivado with an all-English locale did the trick. I had LC_NUMERIC set to "de_DE.UTF-8" and that made it disregard the decimal point.

And the bitstream actually seems to work! I uploaded it via y-modem as I don't have any other interfaces connected yet and the used the "fpga loadb" to load the PL, and I get a 25MHz clock at the phy input. Just to double-check I then loaded the pre-built bitstream from the ebit_z7010 project and the 25MHz clock was missing. So my fumbling around in Vivado actually did something! That is really encouraging!

[CJay]

Good to know, I've got a week off work and a list of projects to play work on, installing and getting started with Vivado is on the list.

[Jope]

there is a $20 Zynq 7010 with onboard SD card slot, USB, HDMI, sound (over HDMI), 1Gbit LAN and 512MB RAM, designed as a devboard. 
[...]
This QMTECH Bajie Board, for an extra $5, looks more tempting to me than a $15 EBAZ2405

Where do you get the QMTECH Bajie Board for $20? In the QMTECH store on Aliexpress it costs $50.

[RoGeorge]

Where do you get the QMTECH Bajie Board for $20? In the QMTECH store on Aliexpress it costs $50.

It was a wrong listed article, now the content of those links I posted for the QMTECH board was changed to show EBAZ4205 boards instead of QMTECH.

ebclr placed an order for QMTECH before the content of the page was corrected, no idea what it was shipped, if anything:  https://www.eevblog.com/forum/fpga/ebaz4205-(zynq-7000-based-development-board)/msg3411322/#msg3411322

[ebclr]

The seller refused to sell and give money back

[thinkfat]

I'm playing around with Vivado and adding stuff to the PL. I notice in the original devicetree there are just two IP instances in the PL, one is a BRAM controller, the other one is a Uartlite core. However, I don't see in the schematic any external connection for the Uartlite. Does anyone have a clue? I thought I could just use on of the fan control sockets, but unfortunately they are connected only to PS pins, not to PL pins.

[thinkfat]

I'm playing around with Vivado and adding stuff to the PL. I notice in the original devicetree there are just two IP instances in the PL, one is a BRAM controller, the other one is a Uartlite core. However, I don't see in the schematic any external connection for the Uartlite. Does anyone have a clue? I thought I could just use on of the fan control sockets, but unfortunately they are connected only to PS pins, not to PL pins.

I made a big step forward and fell into a hellhole. The big step was building my own linux kernel and devicetree and running it on the board. The hellhole was completely trashing the NAND flash with careless use of "nand write" 

I'm now clawing my way back up, but it involves doing things that I'd rather have avoided. Among these are:
- using "Vitis" to create a FSBL that disregards the bootmode resistors and boots straight into JTAG mode
- compiling a working u-boot for the board
- loading the FSBL into on-chip memory via JTAG
- actually modifying the JTAG (extending the CPLD buffer of a DP Busblaster V4) to have a UART on the second FTDI channel (this involves installing an ancient version of the Xilinx ISE toolchain to reprogram a Coolrunnner II CPLD and some VHDL hacking)
- loading u-boot into DDR via JTAG and debugging it with gdb to find out why it doesn't start
- finally getting u-boot to run, using the UART channel of the JTAG to talk to it
- creating a working fsbl-uboot binary, uploading it via serial (y-modem) and flashing it into NAND   <-- I AM HERE

Obviously, I had a lot of fun

[langwadt]

I'm playing around with Vivado and adding stuff to the PL. I notice in the original devicetree there are just two IP instances in the PL, one is a BRAM controller, the other one is a Uartlite core. However, I don't see in the schematic any external connection for the Uartlite. Does anyone have a clue? I thought I could just use on of the fan control sockets, but unfortunately they are connected only to PS pins, not to PL pins.

I made a big step forward and fell into a hellhole. The big step was building my own linux kernel and devicetree and running it on the board. The hellhole was completely trashing the NAND flash with careless use of "nand write" 

I'm now clawing my way back up, but it involves doing things that I'd rather have avoided. Among these are:
- using "Vitis" to create a FSBL that disregards the bootmode resistors and boots straight into JTAG mode
- compiling a working u-boot for the board
- loading the FSBL into on-chip memory via JTAG
- actually modifying the JTAG (extending the CPLD buffer of a DP Busblaster V4) to have a UART on the second FTDI channel (this involves installing an ancient version of the Xilinx ISE toolchain to reprogram a Coolrunnner II CPLD and some VHDL hacking)
- loading u-boot into DDR via JTAG and debugging it with gdb to find out why it doesn't start
- finally getting u-boot to run, using the UART channel of the JTAG to talk to it
- creating a working fsbl-uboot binary, uploading it via serial (y-modem) and flashing it into NAND   <-- I AM HERE

Obviously, I had a lot of fun

no SD card socket?

[thinkfat]

I'm playing around with Vivado and adding stuff to the PL. I notice in the original devicetree there are just two IP instances in the PL, one is a BRAM controller, the other one is a Uartlite core. However, I don't see in the schematic any external connection for the Uartlite. Does anyone have a clue? I thought I could just use on of the fan control sockets, but unfortunately they are connected only to PS pins, not to PL pins.

I made a big step forward and fell into a hellhole. The big step was building my own linux kernel and devicetree and running it on the board. The hellhole was completely trashing the NAND flash with careless use of "nand write" 

I'm now clawing my way back up, but it involves doing things that I'd rather have avoided. Among these are:
- using "Vitis" to create a FSBL that disregards the bootmode resistors and boots straight into JTAG mode
- compiling a working u-boot for the board
- loading the FSBL into on-chip memory via JTAG
- actually modifying the JTAG (extending the CPLD buffer of a DP Busblaster V4) to have a UART on the second FTDI channel (this involves installing an ancient version of the Xilinx ISE toolchain to reprogram a Coolrunnner II CPLD and some VHDL hacking)
- loading u-boot into DDR via JTAG and debugging it with gdb to find out why it doesn't start
- finally getting u-boot to run, using the UART channel of the JTAG to talk to it
- creating a working fsbl-uboot binary, uploading it via serial (y-modem) and flashing it into NAND   <-- I AM HERE

Obviously, I had a lot of fun

no SD card socket?

Yes, a socket. But no card :-( and no chance to get one over the weekend.

PS: back in business. I had a problem with the NAND timing, I had it set way too aggressive and so the FSBL was reading garbage during boot. I have now a FSBL+bitstream+u-boot image in flash again and can start recovering the rest of the system. I'll make some modifications to the partition layout as I go further, I want the uboot environment in a flash partition so that I can make persistent modifications to the boot process.

[thinkfat]

The board is now fully restored. Of course the original flash content (and whatever was in the PL before) is lost. But I managed to piece together a petalinux system that is at least as good as what was previously on the board. Ethernet works, so my modification of the PL to provide a phy clock through one of the PS-PL clocks was successful.

Originally I had a second FCLK generating the 25MHz, meanwhile I've added a "clock wizard" IP block to the PL to generate the 25MHz from the 100MHz AXI clock. But I wonder what is more valuable, the FCLK output or the PL fabric allocated to the clock wizard, which seems to be quite an elaborate thing.

Maybe it's now time to find out how to write my own VHDL code and integrate a simple clock divider instead of the clock wizard. That sounds like a nice first project.

[mgal]

I got the same crystal-less board and built Petalinux and PYNQ from scratch. Now I can program the logic with the ARM core, and I got a python interface along the way. Excellent purchase.
https://webuiltawallwebuiltthepyramids.blogspot.com/

[CJay]

I got the same crystal-less board and built Petalinux and PYNQ from scratch. Now I can program the logic with the ARM core, and I got a python interface along the way. Excellent purchase.
https://webuiltawallwebuiltthepyramids.blogspot.com/

Oh now those blogposts look like they answer a few of my questions.

[dtodorov]

Just received my order of EBAZ4205 after of more than a month of patience.

As I hear commonly a common symptom, it was missing the D24 and after a donor schottky transplant the board became alive, giving it's output on over the UART. The seller was kind enough to provide a TF slot in the plastic bag along with a few 2.54mm headers for JTAG.

Still not sure where to go with this board though. At this moment in life I am not a huge fan of embedded linux, so I plan going bare metal on the board in the coming weeks.

[crossroad]

You can find these boards going for $5 shipped if you find the right sellers. Would there be any sense to reflow off the Zynq chip for use in an actual design?

[RoGeorge]

You can find these boards going for $5 shipped if you find the right sellers. Would there be any sense to reflow off the Zynq chip for use in an actual design?

Where did you found them for $5?  Have a link, please?

[crossroad]

You can find these boards going for $5 shipped if you find the right sellers. Would there be any sense to reflow off the Zynq chip for use in an actual design?

Where did you found them for $5?  Have a link, please?

I picked up 21 of them for 34 CNY each through Taobao iOS app. (Yes I love hoarding stuff)

If you really want a link I can try to get you something but I don't think it'll be easy, I think you need to register with mainland China phone number and stuff.
You should be able just to search for these on Taobao and go through the 30 or so listings for the cheap & legit ones. I'd imagine that these sellers are pretty close to the source of the surplus

Also they came pretty dusty and two had chipped inductors, had to fill bathtub to clean them all. They all worked though

Now the question is if there'd be any sense to reflow off the Zynq chip for use in an actual design

[dtodorov]

On aliexpress they cost as little as $15 including shipping. I am also interested in potential $5 options 

[crossroad]

On aliexpress they cost as little as $15 including shipping. I am also interested in potential $5 options 

I think aliexpress is just an english facing front for taobao, with a pretty hefty markup. I was originally planning to get it from aliexpress but luckily one of my family orders from taobao every few months.

Are there any good resources on getting started with using the FPGA with Vivado? I booted up the software a few days ago and have totally no idea what is going on 

[dtodorov]

There are some github repos, if you follow the links there eventually you can reach some chinese tutorials (google translate kinda does the work)
https://github.com/xjtuecho/EBAZ4205
https://github.com/Elrori/EBAZ4205

[crossroad]

There are some github repos, if you follow the links there eventually you can reach some chinese tutorials (google translate kinda does the work)
https://github.com/xjtuecho/EBAZ4205
https://github.com/Elrori/EBAZ4205

Fortunately I can read chinese! I looked through some of them but it's still hard to make sense of what to do. I've only really had experience with hardware and embedded stuff.

I shelved this little project for now, last time I tried I couldn't get past the "generate bitstream" part in vivado

[dtodorov]

TBH, I am also new to embedded PL+PS systems. This is my first zynq board, but the concept is quite appealing for what I intend to do in future projects.
I kicked-off reading random online docs and youtube videos. These series are kinda good for starters (I recommend x1.5 watch speed    )

[asmi]

Now the question is if there'd be any sense to reflow off the Zynq chip for use in an actual design

I wouldn't use them for commercial designs, but for hobby and maybe prototypes - why not, if you don't mind reballing them and dealing with a chance that they will fail after three thermal cycles (desoldering, reballing and soldering onto a new board).
That said, I'm pretty sure you can find actual chips for a similar price in China if you look really hard, though of course there will be no guarantee that they will actually work either.

[crossroad]

Now the question is if there'd be any sense to reflow off the Zynq chip for use in an actual design

I wouldn't use them for commercial designs, but for hobby and maybe prototypes - why not, if you don't mind reballing them and dealing with a chance that they will fail after three thermal cycles (desoldering, reballing and soldering onto a new board).
That said, I'm pretty sure you can find actual chips for a similar price in China if you look really hard, though of course there will be no guarantee that they will actually work either.

Part of the reason that I trust these xilinx chips more is because they're on these bitcoin boards. I don't think I've came across a single genuine seller from various sample buys - I've gotten fakes of everything from IRFP260, IRFB7730, IRLB8721, to STM32 with extra dimples and logic chips with steel legs.

The thermal cycle thing is a very good point - is the datasheet pretty generous about this like they're just being conservative or do chips really start failing within 3 reflow cycles?

[asmi]

Part of the reason that I trust these xilinx chips more is because they're on these bitcoin boards. I don't think I've came across a single genuine seller from various sample buys - I've gotten fakes of everything from IRFP260, IRFB7730, IRLB8721, to STM32 with extra dimples and logic chips with steel legs.

I'm yet to encounter a single Xilinx FPGA I bought on Aliexpress that was a dud, but there is always a chance for that, and in any case long-term reliability might be questionable because who knows where these chips came from - it could be an "old new stock", or they could be removed from a board and reballed.

The thermal cycle thing is a very good point - is the datasheet pretty generous about this like they're just being conservative or do chips really start failing within 3 reflow cycles?

Well in actuality it means at least 4 cycles, as one more cycle was to mount them on a board in the first place.
The only info I was able to find regarding official Xilinx position on remounting: https://www.xilinx.com/support/answers/7830.html There is also an appnote for flip-chip packages: https://www.xilinx.com/support/documentation/application_notes/xapp426.pdf but I think Z010 devices are all wirebond packages so that appnote does not apply. Basically they are saying - "do it if you have to/want to, but we do not guarantee anything and so you assume all the risk".