You compare the signal to taps with increasing delay, to find the taps between which the edge is.
It is rather complicated way of describing things. Delay line contents is captured every clock cycle of fpga, in my case it's 400Mhz. This creates say 100+ points
of input signal , each of different delay . After calibration this is just equivalent of capture of signal with sampling rate 1/tau = 1/70ps/4 ~ 57GHz
![EBAZ4205 (Zynq-7000 based development board) 1136902-0](https://www.eevblog.com/forum/index.php?action=dlattach;topic=263972.0;attach=1136904;image)
this is the basic structure
![EBAZ4205 (Zynq-7000 based development board) 1136906-1](https://www.eevblog.com/forum/index.php?action=dlattach;topic=263972.0;attach=1136908;image)
delay line with decoder after implementation, marked yellow and green
![EBAZ4205 (Zynq-7000 based development board) 1136910-2](https://www.eevblog.com/forum/index.php?action=dlattach;topic=263972.0;attach=1136912;image)
capture of 125MHz external signal , slowly drifting about own fpga clock..
I have a breadboard/prototype of a "continuous timestamping" frequency counter on my bench which uses an XC7Z010 FPGA talking to TDC7200 ICs to actually sample the input edges.
I could only guess that with TDC7200 you are having hard time counting actual edges. It has large dead time because of GRO . I once tried to implement GRO type TDC , but this was on spartan6 and result was rather noisy.