How to create SPI slave in FPGA when SCLK frequency similar to FPGA system clock

[NiHaoMike]

If the SPI clock isn't continuous (that is is stops between transfers), you cannot really use it as an FPGA clock because all the logic clocked by this clock will stop along with the clock. In this case, create an internal clock which is at least 4-5 times faster than SPI and sample the SPI clock and data as needed.

Or add dummy bytes to let the FPGA finish the SPI operation.

[matrixofdynamism]

The FPGA gets data from an ADC. It will eventually have to pass this into the uC via SPI. Thus, although the primary purpose of the SPI is to make it possible to read write certain control registers inside the FPGA, the design will have to be extended to also transfer several thousand bytes of data from FPGA to the uC.

[nctnico]

You can easely solve that by having one of the SPI readable registers connected to a FIFO (which is fed by ADC data). If the register width is wider than the FIFO you can add status bits to the FIFO read registers telling the reading is valid or not. From there you can add some extra logic to create an interrupt or 'data ready' status (which becomes active when the FIFO is half full or 3/4 full for example) pin connected to an IO pin of the microcontroller. Depending on the datarate you can either simply poll for data or use the interrupt / 'data ready' to read bursts of data from the FIFO once this is available.

[asmi]

Dummy cycles between receiving address and sending out data are often used by high-speed flash memory chips.

[matrixofdynamism]

I will use dummy cycles. The ADC uses source synchronous interface at 120MHz. I will use 60MHz clock to read the DCFIFO and read two bytes at a time instead. This is how I end up with 60MHz system clock for the FPGA design. It is good idea to keep clock domains to minimum really.