First design with FPGA, DDR4 and Hyperlynx SI simulation

[chipeater]

Hello,

For the first time, I'm designing a board with not only an SoC ( Xilinx XCZU4EV-2SFVC784I ), but also DDR4 and fast signals.
I have the Siemens Hyperlynx simulation tool at my disposal but the results seem strange to me.


2 DDR4 chips are connected to the logic part of the SoC and 4 DDR4 chips are connected to the system part. ( All 6 chips are identical ).

When I simulate the logic part, the IBIS model of the FPGA pins is as follows: DWC_D5MQ4_34 or DWC_D5MQ4_34ODT40 depending on whether we're reading or writing.
On the other hand, when I simulate the system part, the IBIS model for the SoC is as follows: HP_POD12_DCI_F_OUT.

The layout constraints for the router are the same for both sections (DDR4 logic part and system part) in terms of single-ended and differential impedances.

And yet, I get the best results by selecting ODT40 for the logic part on the DDR4 side, whereas for the system part, I have to choose ODT120 (almost the same result as with ODT240).
With ODT40 I have 100% fail in data write, problem of exceeding limits in max slew rate and max slew rate 2.

Question:

Does it seem normal to you to have to select 120R ODTs when the data bus is routed to respect a single ended impedance of 40R +-10%?
Or are you thinking more of a Hyperlynx tool configuration problem on my side?

Thank you very much for your help