Are GreenPack SPLDs logic prone to glitches?

[zapta]

When using GreenPak SPLD such as SLG46824, can the LUT generate glitches?  For example, if use a 3 input LUT as an AND gate and the input changes from 110 to 101, can the output have a short '1' during the transition?

I couldn't find any mentioning in the datasheet, compare for example to

[ejeffrey]

Yes, but this isn't specific to these devices. Any asynchronous logic and especially programmable logic can have this. That is why we use flip flops, to only register stable values.

[zapta]

Yes, but this isn't specific to these devices. Any asynchronous logic and especially programmable logic can have this.

Is it?  Take for example the circuit below where a clock passes through a gate to a ripple counter. If the OR gate is implemented with a 74HC32, can a transition on the clock input induce multiple transitions?

In my case, I am asking for the SLG46826 GreenPAK/SPLD, where this schematic is taken from. Is this circuit is safe or can the LUT which implements the OR gate creates more than one transition on a clock transition?
 

[ejeffrey]

That depends on clk1 and clk2?  Do they change at the same time?  If so consider if clk1 can transition 0->1 "at the same time" that clk2 transition 1->0.  If clk1 is delayed relative to clk2 the output of the OR gate can go low transiently.  You can fix this by delaying clk2 relative to clk1 but then the reverse transition is a problem.  Or you can fix it for both by making the falling edge slower than the rising edge, but now you have made a problem for AND gates.  You can work around the problem for a specific case you care about but there is no universal solution.  Since synthesis tools use logical equivalences to map your requested circuit onto the available primitives, it's much harder to solve this by hand for programmable logic.

[zapta]

My question is for the case where clk2 is permanently grounded.

Also, in the case of greenpaks there are no degrees of freedom in the synthesis. The user dictates all the details including which lut instance to use.

[ejeffrey]

In that case I would expect no glitches, or at least for your logic vendor to tell you how to implement it to have no glitches.  That's not the case for your original question which involved two inputs changing at the same time.  In your original question, any asynchronous logic type can have glitches. 

It's not automatic, a LUT is not identical to the logic gate it replaces.  It's actually a multiplexer, and multiplexers can have switching transients. So it is certainly possible for a LUT implementation to have glitches even when a single input changes, but FPGA chip makers should try to prevent that because it's important for a many important FPGA primitives.  For instance it's common to implement clock domain crossing of e.g., FIFO pointers using grey codes so that only one bit changes at a time.  The LUT architecture needs to support that without creating glitches. 

[zapta]

You are right, my original question was AND gate input transition from 110 to 101.  In both cases the output is supposed to state 0. Is that case, do you expect the SPLD to have a glitch (or is it called an hazard?) ?

(I also posted a question at the vendor site and am waiting for an authoritative answer).

[Harjit]

As @ejeffrey mentioned when you have inputs changing into a gate, glitches are absolutely possible.

If you want to run async logic without glitches, a scheme people have used is to convert the state vectors to gray codes where only only one bit changes at a time. Take a look at asynchronous circuit design or dynamic circuits <- fascinating field.

[zapta]

@harjit, in the context of gray code,  let's say that I use a GreenPak LUT as a three input OR gate and its input change from 001 to 011, can this create a glitch at the output of the LUT?

[Harjit]

I cannot say with certainty and do not want to mislead you. You might try it as an experiment. If you do, please do share your findings.

[zapta]

This is the official answer I got from Renesas. If I understand them correctly, they say to use synchronous design.

"Digital has the competition and risk, refer to your design, used the same CLK to trigger the internal states, and the CLK be generated by the falling edge of SCLK_IN, will help to avoid these"

https://community.renesas.com/analog-products/f/greenpak-greenfet/32638/are-slg46826-luts-glitch-free/115464#115464