The VHDL poster you didn't know you need

[hamster_nz]

(Thanks to u/YoureHereForOthers on Reddit)

[asmi]

I know that I don't need this poster. Because I don't need VHDL

[hamster_nz]

I know that I don't need this poster. Because I don't need VHDL

I prefer a language that tells me that I have typoed the signal name for a PCIe TX and RX pair, rather than one that lets you build the simulation, run the simulation for 200us and spent 10 minutes trying to find out why the PCIe link never comes up.   

That's how my day of mixed-language simulation has been... hope your day is going better!

[ebastler]

Boy, do I know I need that chart! 

I have had the page which (I think) is the original source of the chart bookmarked for years, https://www.bitweenie.com/listings/vhdl-type-conversion/. And I am using that bookmark often while writing VHDL...

[asmi]

I prefer a language that tells me that I have typoed the signal name for a PCIe TX and RX pair, rather than one that lets you build the simulation, run the simulation for 200us and spent 10 minutes trying to find out why the PCIe link never comes up.   

That's how my day of mixed-language simulation has been... hope your day is going better!

That just shows that you don't really know that language. Which is typicals of VHDLers.
I prefer a language which doesn't force me to write walls of stupid boilerplate code each time I need to create or instantiate the module, greatly reducing a signal-to-noise ratio of a code, and since code is read much more often than it's written, it trashes efficiency.

[KaneTW]

I prefer a language that tells me that I have typoed the signal name for a PCIe TX and RX pair, rather than one that lets you build the simulation, run the simulation for 200us and spent 10 minutes trying to find out why the PCIe link never comes up.   

That's how my day of mixed-language simulation has been... hope your day is going better!

That just shows that you don't really know that language. Which is typicals of VHDLers.
I prefer a language which doesn't force me to write walls of stupid boilerplate code each time I need to create or instantiate the module, greatly reducing a signal-to-noise ratio of a code, and since code is read much more often than it's written, it trashes efficiency.

I prefer knowing the type of my signal at a glance, vs having to dig through and find the documentation (often wrong) or actual usage.

[ebastler]

since code is read much more often than it's written, it trashes efficiency.

Thing is, I read pretty fluently. But I make errors when I write code. I like a compiler which catches these, and am fine with some redundancy in the written code to enable that.

[SiliconWizard]

(Thanks to u/YoureHereForOthers on Reddit)

Why not. Should be kinda obvious for VHDL developers, but possibly useful for beginners.