DDR3 Data capture using ISERDESE2

[ddr_controller]

I posted a while back that I am trying to make a custom PHY for the Arty A7 35T board. I think I got all the sending commands and writing figured however there is a bizarre thing happening to me with the capture circuit.

In theory, DQS should be delayed in the PHY to center align DQS to DQ however after testing all the possible delay values for DQ and DQS I found the weird thing in the image. In short, CLK is capturing the DDLY that comes AFTER the DQS edge!!! 

The simulation is a Post Implementation timing simulation

Link to the smaller project (only includes the ISERDES part and a TB) here: https://github.com/ESCHen99/test_iserdes