DDR memory READ preamble and postamble

[promach]

1) For Preamble detection and postamble closure for a memory interface controller  , could anyone explain how the following Figure 4 , Figure 5 and Figure  6 work to sample (or capture) the incoming DQ signal during DDR read activities ?

2) Delaying the incoming strobe for READs is more involved and will be covered in detail in an independent technical note.  <-- Do anyone have idea on which exact independent technical note it  is referring to ? I suppose for READ preamble, DQS is aligned with DQ ,  so why need to delay the incoming DQS strobe ? If it is due to DQS  setup timing requirement for sampling DQ signal, then how would I  implement the slight delay in verilog coding implementation ?

[gregben]

First post, so I'm putting on my flame shield!

How about some context? Link to the source of this? I'd like to read more.

I find Figure 6, especially the mux? marked 620 interesting. I fail to see how this circuit would do anything useful unless there are missing details like preset or clear. As shown it would circulate whatever random garbage the flip-flops output on power up.