Hi all,
I have fairly good experience with FPGAs now from the past couple of years. In that time, though, I haven't hit DDR LVDS and deserialisation. In an upcoming project I will be hitting those so would like some pointers.
I'm going to be interfacing with a Sony image sensor that has 4 serial data outputs each running at 297MHz DDR, pretty quick. But I don't think I can use a regular LVDS input on the Cyclone V to do this - it's too fast. But the dedicated transceivers on the GX series require a minimum input speed of 614Mb/s so I'm not quite sure how that works.
Also, all the data synchronisation and validity signals are embedded in the serial data streams which I need to decode. What are the best techniques to go about this?
Thanks for any help.
Boscoe