@Andrp19n, in the VHDL file you send me, pkg_lib.vhd:
Lines 63,64:
PORT_R_DATA_WIDTH: array_of_std_logic_vector(0 to 15)(8 downto 0) := ("010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000");
PORT_W_DATA_WIDTH: array_of_std_logic_vector(0 to 15)(8 downto 0) := ("010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000","010000000");
You have the read and write ports bit width set to 128. Like I said, with a single 8bit DDR3, the maximum you can use is 64, otherwise you will get a compiler error.
The max port width for 16bit DDR3 would be 128 and the max port width for a 32bit DDR3 controller would be 256.
Maybe changing the "binary" representation into an integer would help catch these bugs. On a hunch, I double checked by counting the binary '0's in your code.