So here's a question...
As given, the DDR input/output construct from Gowin doesn't have any obvious built in way to set a different clock on the input and output routes, like the Altera one seems to have.
`timescale 100 ps/100 ps
module Gowin_DDR (
din,
tx,
clk,
io,
q
)
;
input [1:0] din;
input [0:0] tx;
input clk;
inout [0:0] io;
output [1:0] q;
wire [0:0] iobuf_o;
wire [0:0] ddr_inst_q0;
wire [0:0] ddr_inst_q1;
wire VCC;
wire GND;
IOBUF \ddr_gen[0].iobuf_inst (
.O(iobuf_o[0]),
.IO(io[0]),
.I(ddr_inst_q0[0]),
.OEN(ddr_inst_q1[0])
);
ODDR \ddrx1_gen[0].oddr_inst (
.Q0(ddr_inst_q0[0]),
.Q1(ddr_inst_q1[0]),
.D0(din[0]),
.D1(din[1]),
.TX(tx[0]),
.CLK(clk)
);
IDDR \ddrx1_gen[0].iddr_inst (
.Q0(q[0]),
.Q1(q[1]),
.D(iobuf_o[0]),
.CLK(clk)
);
VCC VCC_cZ (
.V(VCC)
);
GND GND_cZ (
.G(GND)
);
GSR GSR (
.GSRI(VCC)
);
endmodule /* Gowin_DDR */
I could, of course, pass in the 2 clocks and just wire up the IDDR to the read-clock and the ODDR to the write-clock. The obvious problem is that the direction control OEN on the IOBUF, which is linked to Q1 on the ODDR, in turn linked through to TX on the input is going to always be in the phase of the write-clock
The question is: does this matter ?
Looking at the signalling for DDR3, it seems there's a whole bunch of cycles before DQ is read/written or DQS* are asserted, and successive READ and WRITE ops will presumably need that preamble, so if the TX is set during that preamble, and held for the duration of the operation, I'll be fine just wiring up the data to the correct clocks, I think.
Of course, I could be wrong about that, and it's also possible that TX is controlled per-cycle, hence the question...