V1.00 FMAX results:
Files, Description:
300MHz, Hypothetical Cyclone III-8 DDR3 System scrolling ellipse build to verify FMAX.
(Uses Quartus 13.0sp1)
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255093)
400MHz, Hypothetical Cyclone III-6 DDR3 System scrolling ellipse build to verify FMAX.
(Uses Quartus 13.0sp1)
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255099)
300MHz, Hypothetical Cyclone IV-8 DDR3 System scrolling ellipse build to verify FMAX.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255105)
400MHz, Hypothetical Cyclone IV-6 DDR3 System scrolling ellipse build to verify FMAX.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255111)
300MHz, functional DDR3 System scrolling ellipse with optional RS232 debug port demo for Arrow DECA eval board, but compiled for a -8.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255117)
400MHz, functional DDR3 System scrolling ellipse with optional RS232 debug port demo for Arrow DECA eval board.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255123)
400MHz, Hypothetical Cyclone V-6 DDR3 System scrolling ellipse build to verify FMAX.
(
![ThumbsDown :--](https://www.eevblog.com/forum/Smileys/default/icon_thumbsdown.gif)
FMAX FAILED
![ThumbsDown :--](https://www.eevblog.com/forum/Smileys/default/icon_thumbsdown.gif)
) Take a look at the multiport clock.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255129)
300MHz, Hypothetical Cyclone V-6 DDR3 System scrolling ellipse build to verify FMAX.
(PASSED, but with I had to disable some smart multiport features and this is a CV-6
![ThumbsDown :--](https://www.eevblog.com/forum/Smileys/default/icon_thumbsdown.gif)
)
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255135)
300MHz, Hypothetical Cyclone V-7 DDR3 PHY Only controller with RS232 debug port build to verify FMAX.
(300MHz only, no multiport ) A CV-7
![ThumbsDown :--](https://www.eevblog.com/forum/Smileys/default/icon_thumbsdown.gif)
, not even a -8. Compiling for a -8 leaves 4 clock domain crossing nets in the red even though the rest of the design including IO ports easily pass.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255141)
375MHz, Hypothetical Cyclone V-6 DDR3 PHY Only controller with RS232 debug port build to verify FMAX.
(375MHz only, no multiport
![ThumbsDown :--](https://www.eevblog.com/forum/Smileys/default/icon_thumbsdown.gif)
) Compiling for 400MHz reveals ~8 clock domain crossing nets in the red even though the rest of the design including IO ports easily pass. In fact, this FPGA should have reached 500MHz.
![](https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/?action=dlattach;attach=1255147)
I will be sending my code to Intel to see why their Cyclone V only gets 60% speed on my multiport commander module. Maybe there is something in the compiler setting to help as the FPGA fabric of Cyclone V is radically different compared to all other Cyclone & MAX FPGAs.
Clocks [ 0 ],[ 1 ],[ 2 ] are the 400MHz DDR_CK, Write clock, read clock.
Clock [ 3 ] is the DDR_CLK_50 200 MHz half speed clock, the interface speed of the Brian_DDR3_PHY_SEQ.
Clock [ 4 ] is the DDR_CLK_25 100MHz quarter speed clock, currently set for the multiport COMMANDER module.