Xilinx DDR Controller Strange Behavior in Sim

[mark179]

Hey guys, I'm having some issues with writing to a DDR controller via an AXI-MM interface. We don't have a board yet so I'm trying to get this verified in simulation.

First, I loaded up the DDR Controller example design (which doesn't simulate because it's looking for some file in a folder that doesn't exist and I'm not sure where it is pointing to.

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ERROR: failed to open /tmp/sim_tb_top.\mem_model_x16.mem.memRank[0].memModel[0].u_ddr3_x16 .open_bank_file.0.
So I'm working with no sim and very little guidance on the DDR Interface, but I pull the test module connecting to this interface and put it in my design in case the thing needs to communicate to work.

No matter what I do, I seem to find wready drop out after the 21st write, whether that is in a huge burst or an 8-word one. I have attached a few simulation images below to show what I mean. oqe1 shows the whole write until it fails on the third transaction, oqe2 shows the first good transaction, and oqe3 zooms in on the third bad transaction. I have temporarily routed bvalid back around to bready just to read the response in my write state, where bresp is now 2. I have absolutely no idea why the write is failing here. Any pointers to guide me in the right direction?

[mark179]

So I ended up fixing this issue some time ago. I had mistakenly set awsize to 7 when it should have been 4... Changing this fixed everything!

[korystoltenberg]

It seems like you're having trouble with the DDR controller simulation using the AXI-MM interface. The missing file error likely points to a memory model file not being found, which is usually generated during the build process. Double-check your project setup to ensure all files are included.

The wready signal dropping after 21 writes may indicate a buffer issue or back-pressure from the controller. Make sure your burst length and AXI settings align with the DDR controller's configuration.

The bresp=2 error suggests an address alignment or memory mapping problem. Since you're routing bvalid to bready, ensure your simulation accurately reflects how the DDR controller works in hardware.

For more insights on related to Sims and registration issues, checking out resources like [spam link removed] can provide solutions from others working with similar setups.