Arrow DECA MAX 10 board for $37

[Daixiwen]

They do work but you'd need to add the _0 in the BASE parameter:

Code: [Select]

IOWR(TEMP_LM71CIMF_0_BASE, WRITE_MODE, 0xffff);  //set shutdown

[RoGeorge]

Now it makes sense, thank you.   

I've dig for a while through the header files like system.h to see the expected names, but I guess this is not the way.

How and where does one find the expected naming without code examples?
Are there any docs specific to each IP, or docs for generic naming rules to follow?

[Daixiwen]

The macros usually just take the component name, uppercase it and add prefixes to generate the different constants in system.h. The actual constants generated can change depending on the IP type, but all IPs have at least the base address declared as *_BASE.
A lot of the IPs available in QSys are documented here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf and some more specialized IPs have their own documentation.

[RoGeorge]

Great, thanks again!
Will browse the doc.

I was trying to find the same pdf corresponding to Quartus v15.1 (the version I am using with the DECA board).  I don't expect big differences, only hoping for a more concise pdf with less pages.

Since the former Altera website is now hosted inside the Intel website, most of the Quartus doc buttons and links are now redirecting to some generic unrelated Intel page.

I was trying to see if there's any doc installed locally, and a search inside the Quartus 15.1 install folder

Code: [Select]

find ./ -iname "*.pdf" | wc -l returned 142 pdf files.   

Xilinx use to have a dedicated tool called Xilinx Documentation Navigator, able to download their documentation locally, and keep track of various pdf versions and their content, the tool was also able to search inside all the pdf files without opening each one.  I've googled and couldn't find if there is something similar for Altera.

Is there any "Documentation Navigator" for Intel Altera, or some other tool similar in functionality with the Xilinx one?



Found another small mismatch in the lesson 4 files.  In "4_Gesture_Sensor_Lab" files, the C and header files starts with capital letter, while inside the code they are written in lower letters, for example inside "Si114x_functions.c" there is an attempt to include "si114x_functions.h", while the provided file is called "Si114x_functions.h".

In Linux the file system is case sensitive, so it won't find that header file.  Same files will probably work OK in Windows (IIRC Windows file system will only preserve the case, but it is not case sensitive).

[RoGeorge]

Found various versions of UG-01085 (Embedded Peripheral IP User Guide).
- 2014.24.07 - 336 pages
- 2015.11.06 - 480 pages
- 2016.12.19 - 538 pages
- 2021.03.29 - 579 pages

It has had more than 40% increase in the number of pages between 2014 and 2015, thought diffing the ToC there's not much difference.

[wilfred]

I ordered a couple of these and my order has been stuck for a week now in "Submitted" status. Is this to be expected with Arrow and I just need to be patient?

I'm in Australia, I paid with Paypal and the funds are not yet withdrawn from Paypal. I am eligible for free Fedex shipping and I got the first order 10% discount. The website lists stock at more than a thousand.

I sent a message and only have an automated reply saying that replies are delayed due to Covid.

Is this to be expected with Arrow and I just need to be patient? Or is there some action I can do to shake things loose. Thanks


Edit: I got a Fedex tracking number today (18th May). That is a delay to ship of about 9-10 days.

[RoGeorge]

For my order (EU/Ro w debit card) it took 7 days for the order to change from "Pending" to "Fully Shipped".
Overall, the board was ordered on 14th and arrived on 26th.

[wilfred]

Thanks. And thanks for your posts here. I'm making notes.

[RoGeorge]

Two more remarks about the DECA board and the workshop:
- both onboard temp sensors are heated by the PCB, so they rather measure the PCB temperature than the room temperature.
- in the "6_USB_to_SDHC_Lab" of the workshop there is an encrypted proprietary IP, with a license file provided in the project's folder.  However, the license is valid up to 2015-Aug-31, so it won't be valid in 2021.  If you just set the datetime year back to 2015, FlexLM will notice the date was set back, and the provided license .dat file still won't work.  I didn't bother to reinstall everything clean like it would be 2015, because the workshop doesn't teach anything new anyway.  "6_USB_to_SDHC_Lab" is more like a demo than like a lesson.  The project can still be run with the already existing bitstream if you unzip the "6_USB_to_SDHC_Lab_Completed.zip" files instead of "6_USB_to_SDHC_Lab.zip".

If any Linux users bother running that 6th lab, it will appear as "SLS USB2.0" removable device (so the new USB device won't need to be added to the udev rules, like the programmer needed to be added to the udev rules).

Code: [Select]

~$ lsusb
Bus 001 Device 005: ID 1772:0002 System Level Solutions, Inc. USB2.0
Bus 001 Device 004: ID 09fb:6010 Altera Arrow MAX 10 DECA



Just for the docs, by default Linux denies access to any place or device that was not explicitly specified as granted access.

Some USB devices, like the removable USB storage type, are already granted by the OS setting (like Ubuntu use to do).  However, for other hardware devices like the JTAG programmer of this DECA board, access is not granted by default.  An udev rule is required in order to grant access to the JTAG programmer, or else the device can only be seen by lsusb, but can not be used.

My udev file "/etc/udev/rules.d/51-usb-blaster-etc-udev-rules-dot-d.rules" added more devices, but for the DECA board only the line for "09fb:6010" should be enough.  This is the content of the .rules file, copied from an online blog I don't recall, sorry for the lack of proper credits:

Code: [Select]

# USB Blaster
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6002", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6003", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"

# USB Blaster II
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6010", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6810", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"
This .rules file is not something for "6_USB_to_SDHC_Lab" only.  The udev file is required for any workshop or demo of this board when used from Linux, or else the JTAG programmer can not be accessed.  No additional drivers required for Linux (in contrast with Windows, which requires JTAG drivers to be installed), but udev rules must be created manually. 

Didn't mention this before because this is the usual thing to do in Linux for any new USB devboard or other unknown USB devices, not just for this DECA board.

[SuperFungus]

Have not tried it yet, but I noticed that there is a tutorial for targeting this board using the Clash HDL: https://clash-lang.org/blog/0006-deca-starter/

[SiliconWizard]

So, anyone here having now experience with the MAX10 and who could share opinions?

[RoGeorge]

I absolutely loved it.  Worth every penny.  Highly recommended to anyone interested in FPGA.

The FPGA is quite generous in size, the board has lots of onboard peripherals to play with, has gesture detector, ADC with analog level shifting (that allows +/- voltage input, not only positive voltage like the usual ADC), accelerometer, humidity sensor, etc.  It even has 512kBytes of DDR3 and can run Linux if you want, and it is built very nicely, with high quality parts.  Even the packaging was impressive.  Also, it's a bargain for that price.

There are some free classes/workshops I found to be very usefull to get one started with this board, and with Quartus IDE in general.

OTOH, it's still an FPGA, so harder to start with than a casual Arduino board, it's a steep learning curve and it's about hardware mostly not about programming like other microcontroller based devbords.  Thought, one can place an MCU core inside, or maybe a few, and write C for them.  Has even a debugger, not like Arduino that still doesn't has a debugger after so many years.

That workshop was very important to follow (I posted links to it here, somewhere in the previous posts), without that workshop to me would have been a more cumbersome start, because I didn't use Quartus before.  Now I like it, honestly I like it more than Vivado, no idea why, sorry Xilinx 

About the Quartus license, the free one is enough, and as a side note, the commercial licenses from older versions can still be used for newer versions of Quartus.

I highly recommend to use the exact version of Quartus used in that workshop if you are new to Quartus, because in the newer Quartus there are a few cosmetic changes in the menus and the naming of those menus than they use in the workshop.  Otherwise the workshop still applies, except one or two lessons where they used a time limited license for a demo hardware IP I didn't care about anyway.

Requires more determination than other devboards, but it's a fun toy to play with, good for both learning or projects.
Go get one, you wont regret!   

[Mechatrommer]

subscribing... why https://www.arrow.com/en/products/deca/~/media/3c3f9da78c4b4b8d880a68fcb7a4e4cf.ashx is blank to me? (linked from https://www.arrow.com/en/products/deca/arrow-development-tools)

[RoGeorge]

Same here, first link is a a blank page.  Probably because the board was launched in 2015, and since then Altera was bought by Intel, and Arrow probably upgraded or migrated their website many times since then.  I remember not all links from arrow were working when I start learning about the board.

Even the wiki pages from the former Altera were moved.  They are still available, but now they are inside the Intel website.  So if you google or find info with links to former Altera, there is a way to translate that links to the current site.  Most of the times it worked, if not try searching for the same words and restrict the results to be from "site:intel.com" only.  I posted somewhere in this thread how to translate the links, but that is only from Altera to Intel wiki pages, no idea how to find the missing Arrow pages.

Anyways, I remember most of the Arrow links were pointing to the same info that can be find either in the CD that can be still downloaded from Terasic (they manufactured the board), Altera wiki or Intel.

What was the text you clicked for that blank page?

[steamedhams]

Has anyone found a camera that works with this MIPI connector? 

[Mechatrommer]

What was the text you clicked for that blank page?

its in the line where..
"Getting Started:
Click here to download the DECA lab materials.  Includes software and hardware lab manual and source files."

i'm like a baby expecting to be spoonfeed here. i expect some place that teach me everything from downloading what IDE to use, some hello world example and then what device/programmer and how the connection to do programming, exactly like arduino guide for dummy. i bought china fpga dev kit module few years ago for pennies but never got into the game ever, mostly i think due to many other tasks to do and enthusiastic to learn fpga is very downhill due to lack of these fpga for dummies guide, or i may not search hard enough or never found it... i can print a vhdl/verilog book however thick they are to learn the programming but what for? if i cant get the toolchain right (transfer the code to hardware) i might be lacking some programmer hardware that i'm not aware of then i might be chasing my own tail..

from time to time i browsed some fpga dev kit but they are unreasonably expensive, let alone the license and IP legal issues on SW/IDE side which makes things look scary... i downloaded few version of quartus trying to get acquainted but never got a clue, hence i have few GBs of idle storage here storing them.. now this deca dev kit is very teasing at much less than $50, but then, its not available where i used to purchase online (i'm not sure if i register in their website, if they even want to ship to my country) and its official dummy guide is missing. i can see some guide links in this thread thumbs up, i will get back to this... i'm sorry for myself, who else?... so i'm just subscribing here to get the latest update, not much more... this thread is few months already but i missed it, how ironic?...

[RoGeorge]

What was the text you clicked for that blank page?

its in the line where..
"Getting Started:
Click here to download the DECA lab materials.  Includes software and hardware lab manual and source files."

Don't know what it was there, but the main links to start with this board could be this one instead:  https://www.eevblog.com/forum/fpga/arrow-deca-max-10-board-for-$37/msg3559571/#msg3559571



Download and install http://Quartus 15.0, not newer or else the workshop lessons won't match with the IDE, then try this workshop and see if it makes sense:
https://community.intel.com/t5/FPGA-Wiki/DECA/ta-p/735458

There are a few more links in the workshop wiki page, but the workshop I am talking about starts somewhere in the middle of the webpage, where it says:
"

Workshop Reference Designs
Lab 1: FPGA Intro Lab

    A step-by-step guide to FPGA design using Quartus II

"

Read the Lab Document PDF, then try to practice on your installed Quartus, even without the board, to see if it makes sense for you.

To program this board you don't need an external programmer.  The board has an onboard JTAG programmer and a USB cable.  Plug the USB and that's it, to program the board just click the right menus from Quartus (it is explained how in the PDF).

[BrianHG]

All software DDR3 controller update....

16 read, 16 write ports with smart cache, configurable priority encoding and data width per port done.
4096x2160 screen scrolling on a 1080p 32bit color out HDMI with geometry test drawing program done.
Auto DDR3 PLL calibration finally done.

  !!!400MHz with data integrity!!!   With a +/- 3 PLL tuning step valid data window.

Yes, Altera/Intel's software DDR3 solution is only rated at 300MHz.  Not even the minimum 303MHz rated by the DDR3 spec.
It also only has a single read and write port.

It's Altera's hardware dependent PHY which has multiport and runs at 400MHz.

Things left to do:
Upgrade my software FIFOs in my multiport module as they currently have a bottleneck of 125MHz because of the way they are written.
Improve the cross clock domain boundary as the DDR3 sequencer sends commands to the DDR3 CK clock domain.  (The solution I'm looking at might get the DDR3 running at 500MHz on a -6, but definitely working at >300MHz on a -8, even on old Cyclone III & IV.)
The goal for the above 2 is at least 300MHz allowing for a 'Full Rate' controller where as if you want the 400MHz (officially overclocking Altera's IOs), you will probably need to run it at 'Half Rate', or 'Quarter Rate'.

Without the Multiport module, IE, directly communicating with my DDR3 controller, 1 read & 1 write port, the controller consumes just under 3K logic gates for a 16bit DDR3 ram chip.  And it is smart, keeps banks open and aware when you access across banks, it will keep banks open if it can, only close and open individual banks as it needs to.

I should be ready to post the source next week.

[andybrandi]

The Arrow.com shop is asking for a valid VAT ID, even when ordering as a private customer. Is there any way to get around that?

[RoGeorge]

Somebody else from Poland was asking about the same thing on PM.

I didn't need a VAT ID three months ago when I bought mine, but it seems something has changed since then.

[BrianHG]

This is just a test demo of my DDR3 controller with 32 bit color 1080p display and a ellipse geometry drawing processor.

I have attached 2 demo files for to test in the .zip archive.

They are .sof programming files, so, all you have to do is:
Open the Altera programmer,
Select the DECA JTAG programmer,
Make sure the programmer is set to JTAG mode.
And add only 1 of the files and program.

There are 2 files, a good one and a lemon one.

The good one should generate a picture holding a 32 megabyte 4096x2160x32bit bitmap.

Switch 0 should enable/disable the drawing of ellipses.  (Power-up with the ellipse draw disabled and see what the DDR3 ram's memory looks like un-initialized.)
Switch 1 should enable/disable the scrolling over the 4096x2160 bitmap on the 1080p output.

Button 0 should render random static into the bitmap.
Button 1 should render a colored test pattern into the bitmap.

Please inspect for any garbage around the left&right border carefully as it draws.  I need to use a 30 foot HDMI cable because of my setup location and that cable leaves speckles throughout my picture.  The output should be clean but I cannot tell for sure if there are buffer under/over-run bugs while drawing, but it does look perfect.

The lemon file should make a red-orange-green pattern.  If so, I have a coding bug.  If it draws the ellipses at half speed, then my coding is good, but, I have a lemon FPGA.
I tried re-compiling in Quartus 15.0, but, there it crashes right at the last 'assembler' step.  (Besides compiling really slow compared to Quartus Prime.)  I'm downloading Quartus 15.1 to see if it crashes.

If anyone is willing to wire up the RS232 for use with my RS232-Debugger code here: https://www.eevblog.com/forum/fpga/verilog-rs232-uart-and-rs232-debugger-source-code-and-educational-tutorial/msg2801388/#msg2801388

This is the wiring:
TXD out of the DECA board to PC is on pin GPIO0_D[1].
RXD into DECA board from PC is on pin GPIO0_D[3].

The contents on 'In0' at the bottom left of my debugger is of use to me, but not crucial.

Please let me know the results.


In the lemon file, the DDR3 is still working fine as the RS232-Debugger can read and write to it, but, the read-requests on the display port are being dropped or ignored and it should work fine.  The bug is affecting my multi-port module, but all I did was run the section at 1/4 speed instead of half speed.  Cycling the software reset in the RS232 debugger sometimes brings up a frame on the display, but it then dies instantly and yet it simulates properly.  This is a fishy problem where multiple command FIFOs and selection priorities interact and there isn't an effective way to simulate the millions of cycles to generate the crash in Modelsim.
There are other weird sings where some compile builds fail to do anything just by changing a simple parameter or compiler option which should have no bearing on the functionality, so I am wondering what is going on.

It should take a few more days to find this bug, then I will release the full source code on a new thread here.

Link to patched V2 code: https://www.eevblog.com/forum/fpga/arrow-deca-max-10-board-for-$37/msg3601248/#msg3601248

[BrianHG]

Ok, after a report on both demo files failing to show the ellipses on someone else's DECA board, it appears my multiport code is unstable as it seems to completely seize up when receiving too many requests too fast.

You would think this shouldn't be able to happen.  Though, I did manage to get my code to compile in Quartus 15 and it also seized up.  So much for this warning:
'Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary'

Preliminary?  Compiled with Quartus 20.1.  Still? For a 5 year old FPGA?


Note on the blue status LEDs:
LED4 = reset released and PLL is locked.
LED2 = DDR3 controller read calibration has passed and the DDR3 is ready to use.
LED5 = Power-up initialization complete, DDR3 ready to use.

If these 3 LEDs are on and you only see the junk red-orange-green test pattern, then it's my multi-port code which has seized up.  It looks like it may be a cross clock domain meta-stability issue which wont show in my Modelsim simulations.

[RoGeorge]

'Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary'

Preliminary?  Compiled with Quartus 20.1.  Still? For a 5 year old FPGA?

IIRC from the datasheet there's no -6 speed grade commercially available.

I took it as being some sort of engineering sample.  It will make no sense commercially to fully characterize something that will never be available for sale.  It will always remain preliminary, never guaranteed, only good enough when using -6 speed grade to develop designs that will be deployed on lower speeds grades only.

[BrianHG]

Ok, this version of the DDR3 demo should work.

I've included a build in Quartus 15.0 and Quartus 20.1.

If anyone sees the lemon red-to-green failure image, please let me know which build failed and which blue LED #s were lit up.

Attached files below.


Really had to make individual latched nets for some control signals which cross clock domain boundaries.  A bunch of them.  If these demos work, then there is just some cleaning up to do and I will be ready to post the full source code & examples.


(If the picture is still or scrolling noise, just flip 'Switch 0'.  You just powered up the demo in frozen picture mode and you are looking at the powered up random blank memory.)


Switch 0 = Enable/Disable drawing of ellipses.
Switch 1 = Enable/Disable screen scrolling.
Button 0 = Draw data from random noise generator.
Button 1 = Draw color image data from a binary counter.

[Wiljan]

Image is corrupted see attachment,  connected to a DELL P2419HC it does report 1920x1080 60Hz
Tried on a LG C9 as well ... same image

LED 2,4,5 does lit on both files when loaded with Quartus 15.0 programmer