Altera FLEX 8000: Extracting "bitstream" from .sof file?

[TomS_]

I've acquired an Altera FLEX 8282A FPGA and I'd like to have a bit of a play with it.

Yes, I know these are prehistoric parts, but I like playing around with old stuff. :-)

I've installed MAX+Plus II and have managed to compile a very simple design (a clock divider) for testing purposes.

I have no re-programmable configuration devices, nor any other compatible programmers, so I'll make something myself using a PIC microcontroller. The programming protocol seems quite simple and was well documented by Altera themselves. I'll likely use the serial method of configuration, with the PIC acting like an Altera configuration device and running the show.

What doesn't seem to be so well documented is how to extract the "bitstream" (?) from the resulting .pof or (maybe more probably) .sof file.

I've written some simple Python to parse my way through the .pof/.sof files and extract each "packet" including the one which looks to contain the bitstream, but there's a problem with both of them.

Altera Application Note 33 says the bitstream for an 8282A should be 40000 bits, or 5000 bytes. From the .pof I extract 5120 bytes, and from the .sof I extract 4703 bytes.

So my question is: does anyone understand what you are supposed to do with a .pof or .sof file to program a device? Which part of the longer .pof data do I take, or what do I fill in for the missing part of the .sof?

I think that I should be using a .sof as these seem to be for volatile devices (.pof for non-volatile devices), but the number of bytes are coming up short from what I'm expecting.

Thanks!

[joeqsmith]

If you can't find the old programming manual or sort it out, I may be able to help out once I return home as I wrote my own programmer for these devices.  It's been too long and I am not sure what I was doing off the top of my head but it seemed you could produce a hex or binary file.   I'll get back with you.

[joeqsmith]

You may find a clue in this video.  It appears at 6:57, I am showing a HEX file.  This is what I was loading in.   

[TomS_]

You may find a clue in this video.  It appears at 6:57, I am showing a HEX file.  This is what I was loading in.

Thanks! I'll check this out.

I do have a copy of the document that describes the programming protocol, it's just a question of what data I need to send at it, but this is clearer now...

I have been doing some more digging and reading in the meantime and I think Ive come up with the following conclusions so far:

* I didnt see it earlier, but the 40000 bits is an approximate, so being a little over seems like it should be ok
* I found an option to produce a .rbf from the .sof, and it came out at 5120 bytes
* The .hex file also seems to contain the same contents as the .rbf, and there is also a .ttf with contents that could be #included into a C or assembly source file for example. With those 3 having the same contents, and AN33 mentioning that the .rbf and .ttf can be loaded directly in to the FPGA, I think that is exactly what I need.

The "bitstream packet" in the .pof is 12 bytes bigger than the .rbf etc files, but it looks like after the first 12 bytes the contents are the same as .rbf etc, so perhaps I just need to ignore those first 12 bytes, whatever they are for... Or just use the .hex which is produced by default. 

[BrianHG]

If I remember, the .sof is used for Altera's programmer.  It is the Static Object File, meaning for FPGAs, you can live power send this and run the FPGA, but the program will be lost with power.  The .pof, Programming Object File was Also used by the Altera programmer to burn the FPGA's flash memory making the program permanent.

For third party programmers, I do not know how they went about it.

I used to use the .rbf file when I created my own self-programming firmware updating FPGA code.

[TomS_]

Hi Brian.

Yeah, the thing that confuses me about the .sof and .pof is that the data contained within them is *very* different. By a few hundred bytes or so.

But the .rbf file I generated came from the .sof, so maybe its compressed or is somewhat interpreted and expanded out into a fuller binary image before loading by the Altera tools.

[BrianHG]

You can disable bit-stream compression within quartus.  The feature should be in the same settings tab as the option to generate the .rbf files.

The bit-stream compression was typically used for the .pof files so that you might get away with a smaller boot-prom.  IE: The decompression happens inside the FPGA, not the programmer's software that loads the .pof and decompresses it before burning it.

I am unaware if the older FLEX FPGAs supported bitstream compression, or, if they did, it would probably be simple RLE type which would remove large swabs of repeating 0's or 1's.

[TomS_]

The tool I am using pre-dates Quartus - it's MAX+Plus II.

I think the FLEX 8000's are too old to be supported by Quartus? Or maybe they need a very very early version.

Quartus would be nice though, its a nicer tool overall.

[TomS_]

When I initially tried to target a FLEX 8000 it complained that it wasnt covered by the unlicensed version. But the copy of MAX+Plus II that I downloaded from archive.org contains a license file that seems to unlock everything.

[BrianHG]

If your board is wired in JTag mode, then Quartus' programmer might be able to program the bootprom, so long as your programmer supports 5v.

As for the .rbf file, that one just goes into the serial prom, in order, no bytes altered in any way.

[joeqsmith]

Looking at my old PC,  Quartus 2.1, did not support the 8k series. 

With MaxPlus, if you did not want to use their schematic entry or AHDL (Altera HDL),  I thought they had provided a stripped version of Exemplar Leonardo Spectrum.   It looks like the last version I installed, they had rolled Max+plus II Advanced Synthesis. Do you have this synthesizer installed? 

[TomS_]

The version of MAX+Plus II I have (10.2) lets me write Verilog, albeit a much much older version of it. I was also able to download Advanced Synthesis from archive.org and have installed it as well, although I havent quite worked out what/how that is supposed to do/work yet.

[BrianHG]

The version of MAX+Plus II I have (10.2) lets me write Verilog, albeit a much much older version of it. I was also able to download Advanced Synthesis from archive.org and have installed it as well, although I havent quite worked out what/how that is supposed to do/work yet.

Modelsim available with Quartus, or , a separate download from Intel's site should work without Quartus if all you need is to compile and simulate code.  Though wont get FLEX megafunction libraries like PLLs (unless they are the same as some newer FPGA).  My simpler GitHub code examples have example .do setup and re-compile scripts.

[joeqsmith]

The version of MAX+Plus II I have (10.2) lets me write Verilog, albeit a much much older version of it. I was also able to download Advanced Synthesis from archive.org and have installed it as well, although I havent quite worked out what/how that is supposed to do/work yet.

Outside of AHDL, I don't remember of any other text language support.  Which was why they (and other suppliers) started to bundle stripped 3rd party synthesizers.   Eventually they offered the  Advanced Synthesis tool which added Verilog and VHDL.   I really liked using AHDL as it was a sort of mixed bag. 

Of course, I want to qualify my posts with this is based on memories from the 90s.   

[TomS_]

Sometimes memories are better kept as memories. 🤣

I was able to compile Verilog even before installing Advanced Synthesis, so maybe later versions had this all built in.

I opened up Advanced Synthesis and had a quick look and it seemed to be a really basic text editor and not much else. There's probably more to it that I haven't figured out yet

Verilog in MAX+Plus II is a lot like older C where you list your signals in the module definition, but you declare them as inputs or outputs within the module itself.

MAX+Plus II seems to be fairly full featured, although the simulator needs some getting used to.

[joeqsmith]

Manual for it is available.

http://www.pldworld.com/_altera/html/_sw/max2syn/ug_mp2as.pdf

It does say to use it in place of the built in one.  I fired it up and indeed it does include it.  Looking at 6.0 (1995) it has support for VHDL but not Verilog.  Looking at 8.3 (1998), they have added Verilog.  So it was in there long before 10 was released.

Looking at Xilinx tools from that time frame (Foundation 1.5-3) they appear to be using FPGA Express / Synplify.  Lattice tools appear to be using LeonardoSpectrum and Synplify.  Too many tools over the years clouds the memory.    

[Tation]

MAX+plusII did, definitely, support also VHDL. I didn't remember, though, from which version nor do I still have installers.

[joeqsmith]

MAX+plusII did, definitely, support also VHDL. I didn't remember, though, from which version nor do I still have installers.

As I already wrote, it did as of version 6.   Going back to MaxPlus, I don't believe it ever did.   

Having a look at older MaxPlusII that still supported the 8k series but did not support for VHDL or Verilog.  AHDL and schematic only.   They did however allow third party synthesis tool to create an EDIF which could then be imported to MaxPlusII.  This is what I was doing with Xilinx as well.   So, somewhere between 1993 and 1995 they added VHDL.   Memory served me well I guess.     

[TomS_]

An update, Ive managed to successfully configure the EPF8282A that I have as an example part.

The .rbf file is literally just something you can clock straight in to the FPGA (LSb first), and then a few more clocks after that to initialise it and set it running.

For the .pof file, I parse this to find packet type 7 ("Electrical Address and Data"), and then skip the first 12 bytes and load the remainder of the contents in to the FPGA (LSb first again), and again followed by a few more clocks to get it running. Im not sure what the 12 bytes are that I have skipped, they dont seem to have any meaningful values (e.g. length of the bitstream etc) or easily discernable purposes, and they are not documented anywhere that Ive found yet, but the method seems to work just fine.

As for .sof, this must have some kind of compression, so I am ignoring this and concentrating on .pof since this is generated by default by MAX+plus II when compiling a design (generating a .rbf requires additional steps).

Ive implemented the loader function in to a PIC microcontroller with an external SPI flash as I had originally planned, and so far it is working great - configuring the device on power up completes quicker than the blink of an eye, and loading over serial takes less than a second. 

[TomS_]

And Ive now managed to successfully configure an EPF81188A as well. I put together a dev board for it, worked out of the box! 

I maed a little game with it - you are displayed a hex digit, and have to respond with the corresponding binary through some buttons. Theres a little scoreboard that shows how many correct answers youve given in a row, and a speaker gives some audible feedback of correct or incorrect answers. Theres a little video of it here: https://photos.app.goo.gl/BmLpgExfwWqw37iv5 

[free_electron]

you get an altera Byteblaster and you don't need to muck with pof and sof files.
as i remember one is the file you need to store in a flash memory ( configuration memory. which is actually a 25128 spi-memory), the other one can be stored in the flash of your microprocessor and loaded from there using the JAM player. ( simple protocol to send bitstream into the fpga. )