Basic Serializer Verilog

[beginner43]

Hello everyone. I'm new to Verilog. I want to convert a parallel data to serial, but without success. What are the bullshit and flaws in my code?
----- TOP------------------
`timescale 1ns / 1ps

module Serializer(
    input  wire clk,
    input  wire [7:0] in_data,
    input  wire valid_data,
    output reg out_data
    );
       
    reg [7:0] temp_data;

    always @(posedge clk)
    begin
    temp_data <= in_data;
        if(valid_data == 1)
        begin
            temp_data <= {1'b0, temp_data[7:1]};
            out_data <= temp_data[0];

        end
       
    end
   
   
endmodule





-----TESTBENCH-------------
`timescale 1ns / 1ps

module tb_serializer();

reg tb_clk = 1'b0;           
reg [7:0] tb_in_data = 8'b01010011;
reg tb_valid_data =1'b1;
wire tb_out_data ;     

//Clock
always begin
tb_clk = ~tb_clk;
#5;
end

//Testbench Connection
Serializer DUT(           
    .clk(tb_clk),         
    .in_data(tb_in_data),
    .valid_data(tb_valid_data),   
    .out_data(tb_out_data)
);                     

//Serializer

initial begin
#200;
tb_in_data = 8'b11001111;
end


 
endmodule

[pcprogrammer]

    always @(posedge clk)
    begin
    temp_data <= in_data;
        if(valid_data == 1)
        begin
            temp_data <= {1'b0, temp_data[7:1]};
            out_data <= temp_data[0];
        end
    end

I'm no expert, but I think it has to do with the fact that on every clock you load the "in_data" into your "temp_data" undoing the shift.

To make it work you have to latch the data into your "temp_data" first and clear a flag to switch to serializing. So load on the first clock and then shift on the next 8 clocks.

[BrianHG]

Also, in your simulation testbench, you are not driving ' input  wire valid_data,'.
Your code does nothing without it.  Also make sure your stimulus first loads the parallel data into the temp for a clock cycle, then hold the 'valid_data' high for 9 clocks.

[josuah]

            out_data <= temp_data[0];

Maybe this could be simplified a bit by making this an assign statement?
The out_data would no more need to be a register, but a mere wire.

Having it a register would delay the output by one clock, but maybe this was on purpose.

[josuah]

module Serializer(
    input  wire clk,
    input  wire [7:0] in_data,
    input  wire valid_data,
    output reg out_data
    );
       
    reg [7:0] temp_data;

    always @(posedge clk)
    begin
    temp_data <= in_data;
        if(valid_data == 1)
        begin
            temp_data <= {1'b0, temp_data[7:1]};
            out_data <= temp_data[0];
        end
    end
endmodule

So on every "incoming request", marked by valid_data I supose, you are shifting temp_data (a shift register) by one clock?
Do you not want that to happen on every clock instead of just when new data comes in?

[EDIT]:  It looks like I am saying the same thing as pcprogrammer with different wording.