My current attempt to create a testbench for a led blinker module:
`timescale 1ns / 100ps
module Clock();
reg sysclk = 0;
initial begin
forever begin
#10 sysclk = ~sysclk;
end
end
LedTest ledTest(sysclk, led_0);
endmodule
Am I doing it properly?
It should create a clock with a period of 20 ns. But what is led_0 ?
Without knowing what led blink does and what led_0 is, it may be enough or not.
The idea of the testbench is to exercise the logic, the fsm and so on. To try corner cases. To see if the given module does what you think it does
![Smiley :)](https://www.eevblog.com/forum/Smileys/default/smiley.gif)
, it can do more too.
I'd recommend you always define all your signals. You can also use following directive
`default_nettype none
to force undefined signals to not have a default "wire [0:0]" definition, it helps finding some mistakes, specially when you forgot that the wire may need to be wider than 1 bit !.
I'd recommend you always define all your signals. You can also use following directive
`default_nettype none
Thanks, good idea. Strangely, with this directive on Vivado shows a hint in the editor, but still compiles the code without any warning. I wonder if it's possible to make it fail synthesis in this case?