FPGA

How modeling static RAM in Verilog

« 1 2  All »

Re-programming Secure Microchip ATF150x series CPLD devices

Vivado (Xilinx) - Is there a way to store project information on GIT?

does exist a mirror of ftp.altera.com?

Programming (non-JTAG) MAX7000 devices

« 1 2 3 4 5 6 ... 10  All »

Lattice CrossLink FPGA configuration using I2C

Modelsim Altera Edition 6.4a from Altera Quartus II 9.0

Small footprints with 'many' min 12G tranceivers

Advice for my graduation project

Help with my first IIR biquad (DF1)

New TI tiny PLDs (TPLD)

« 1 2  All »

TL866II Plus and Lattice GAL22V10D

ACTEL Activator 2S - APSW software needed

Salvage board for sale on ebay

Interfacing FT232H to FPGA in FIFO Synchronous mode; 1 clock wide TXE# pulses

Tang Nano 9K issue with FF

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

« 1 2 3 4 5 6 ... 15  All »

How to convert a 16-bit unsigned to 16-bit signed for multipliers

Digital Oscilloscope Design with FPGA

« 1 2  All »

am I the only one who thinks Vivado/Vitis is a muddled mess?

« 1 2  All »

Intel/Altera ROM megafunction

RapidSilicon - what happened to "open-source" FPGAs ?

Pull-up/pull-down resistors

JESD204B over fiber

SD card/SDIO 3.0 level translation solution

« 1 2 3  All »

Microchip - what the heck is going on with PolarFire II ?

XC9500XL : using "Timing driven" macrocells power setting

Multiple MIG controllers clocking

FPGA for beginner

« 1 2  All »

UART recommendation? Verilog/VHDL, supports 2 stop bits

Flash backed LLMs on FPGA?

Xilinx DDR Controller Strange Behavior in Sim

Avnet for Xilinx XC3S400A

I need to get my head around timing (Xilinx)

Maximum utilisation

Calculateing the size of a pipeline vector

The Blair Witch story of my first FPGA devboard made from a printer front panel

IC configuration approach - Hardware vs. software

Vcd Viewer (VcdView) upgrade available (now with equations)

YoSys: status?

« 1 2  All »