Logic for WVALID and AWVALID in AXI Master

[promach]

For this AXI master coding, how do I guarantee AW* payloads are sent first, followed by W* payloads without violating AXI protocol (a master must not wait for AWREADY to be asserted before driving WVALID) ?

Code: [Select]

    always @(posedge clk)
    begin
        if(reset)
        begin
            o_axi_wvalid <= 0;
        end
     
        else if(!(o_axi_wvalid && !i_axi_wready))
        begin
            // Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
            // since this is for testing, WDATA just uses some values up to the total size of the write address space
            // see [url]https://i.imgur.com/LBO9pQz.png[/url] in which AW* payloads are sent first, followed by W* payloads
            // Note: a master must not wait for AWREADY to be asserted before driving WVALID
            o_axi_wvalid <= (o_axi_wlast) ? 0 :
                            (o_axi_wdata < (o_axi_awsize*o_axi_awlen)) && o_axi_awvalid;
        end
    end

[asmi]

Not sure I understand the question. Typically you will have separate states of your FSM for AW and W stages. The way it's supposed to work is as follows: you place the data on a bus and assert *VALID signal. Then you keep this data until *READY is also high (AXI mandates than once you set your *VALID signal, you are not allowed to change anything on a bus until transfer occurs), then you advance your FSM to W state (AXI states that transfer only happens when both *VALID and *READY signals are high on the same clock edge). You've got to remember than when you set some signal via non-blocking assignment, it will only become "visible" to receiver on the next clock edge, so you can't check *READY signal at a time you're asserting *VALID and assume it will be the same on a next clock edge, when the transfer actually occurs.
Also - for the last transfer in a burst you've got to assert both *VALID and *LAST signals.
Finally, if you use Vivado, I highly recommend to use AXI Verification IP as it both helps to stimulate your AXI bus interfaces using very simple SV code, as well as to verify that transactions your module is performing are AXI-compliant (it will halt the simulation if it observes any activity on any AXI channel that is not compliant to the specification).

[promach]

In the pc_status error bit location , is it bit #32 because in the following simulation waveform, BVALID is never asserted high during the time when pc_status error bit #32 is asserted ?

[promach]

Ok, I have solved the above pc_status[32] AXI_ERRS_BRESP_WLAST error.

Now, I have an entirely different pc_status[22] AXI_ERRM_WSTRB issue.

Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and Beat Number.

What does it mean by The information on the low-order address lines must be consistent with the information on the byte lane strobes. ?