Low purity what, recovered copper is electrolytic grade.
Also, are you just assuming, or do you have data from operating fabs?
![Huh? ???](https://www.eevblog.com/forum/Smileys/default/huh.gif)
In either case, it's
down in the noise for the cost of fabbed boards. Unless you're doing millions, what's it really matter?
![Smiley :)](https://www.eevblog.com/forum/Smileys/default/smiley.gif)
I regularly do 2-layer boards with dense layouts, this one for example:
https://www.seventransistorlabs.com/Images/LimitingFusePcb.jpg (I don't have a 2D view handy; there are a few traces on the back, routed to carefully avoid cutting off the ground plane between top and bottom.) Though I wouldn't say these sorts of layouts are "typical" in commercial use.
Back in the days of 1-layer boards, the next best thing was ground generally poured around everything, using jumpers to close loops only where absolutely needed. Also, they made a lot of boards suspiciously like they were either saving etchant or maximizing conductivity (which may well be important with the typical 0.5oz foil?). An aside, I never did understand how they made those; they were made in the CAD era, not freehand taped, but I've never seen an EDA that draws in negative space exclusively. Possibly some Japanese exclusive.
(Not that 1-layer boards are gone, they're still quite common in power supplies. These days, most products seem to be complicated enough to need multiple layers, or whole ass planes for signal quality alone. Which is understandable, given the ever-higher density and flexibility of MCUs and whatnot.)
Tim