Can you specify trace *thickness* in your EDA software?

[MagicSmoker]

A new capability being rolled out by some of the more prominent "heavy copper" board houses is the ability to selectively plate thicker copper onto specific traces so that control and power circuits can be on the same board. For example, all of the control circuit traces can be the standard 1oz / 35um thick Cu while high current traces can be plated up to 20oz / 0.7mm. This is a fantastic thing for those of us who concentrate on power electronics, but I suspect few, if any, EDA programs will let you set the trace thickness for specific traces, nets or planes. So, I'm basically asking if this functionality is actually available?



* - EAGLE v7.7; yes, I'm one of those holdouts refusing the AutoDesk borgification.

[SiliconWizard]

I personally don't know of any EDA software that would support this. Maybe there is.

This is how I would handle it so I'm not relying on any specific feature: I would create an additional layer for each layer that requires this selective plating, and copy onto it the traces that need to be plated. I would name the layer with the same name as the original layer, and add a "-plated" suffix or something.

Then of course I would attach a fabrication file listing all the Gerbers and their roles, stating what those extra layers are for, what's the expected plated thickness, etc.

Can be done with any software that allows selective copying of traces from one layer to another (many do), and for the PCB manufacturer, getting the information as additional Gerber layers is probably completely usable.

Just a thought.

[MagicSmoker]

Well, that's sort of the idea I had - redrawing traces, pads and vias (or copying them, though this has a higher risk of suffering unintended consequences) on an unused documentation layer (e.g. - 48). Otherwise, perhaps a Z-axis movement G-code could be pressed into service here as a trace thickness designator - so, something done in post-processing.

Erf... I just realized that differing trace thickness will likely cause problems with pick-and-place machines, too...

[SiliconWizard]

(or copying them, though this has a higher risk of suffering unintended consequences)

Not sure why? What kind of consequences?

Of course, in both cases, the downside is that if you modify the original traces, the additional layers need to be updated accordingly, which is a bit annoying and error-prone.
But I'm sure that getting the info as extra Gerber layers is perfectly usable for the manufacturer. I think that would be the option with the least chance there is a fuck-up (of course as long as all your layers are properly aligned.)

Erf... I just realized that differing trace thickness will likely cause problems with pick-and-place machines, too...

I wonder how that's dealt with in practice.
I have never had to design such a PCB, but my first guess would be to make ALL pads the same thickness regardless of the thickness of individual traces. I don't know if it's the right way of doing it or if it's even possible with the current processes.

[MagicSmoker]

(or copying them, though this has a higher risk of suffering unintended consequences)

Not sure why? What kind of consequences?

EAGLE won't let you copy traces and pads without severing back annotation first, so that only leaves redrawing the pads, traces, etc., on the unused layer which is ripe for making mistakes since you don't have the benefit of using the package libraries anymore.

Erf... I just realized that differing trace thickness will likely cause problems with pick-and-place machines, too...

I wonder how that's dealt with in practice.
I have never had to design such a PCB, but my first guess would be to make ALL pads the same thickness regardless of the thickness of individual traces. I don't know if it's the right way of doing it or if it's even possible with the current processes.

Making all the pads the same thickness wouldn't allow you to mix small SMD components on the same board as power components because the trace/space riles need to be much more forgiving as the copper thickness goes up. The only real solution I've come up with is that the P-n-P machine operator would need to program in a custom Z offset for the components placed on the heavy copper pads. But again, I have no idea if this is something the typical P-n-P machine can accommodate without significant operator intervention and/or kludging.

Oh, and I thought of a real show-stopper - you can't use a stencil printer to apply the solder paste. Erf, applying paste to each pad individually - even if using a (semi-)automatic dispenser - is no fun at all.

[Mattylad]

I would simply add an attribute to all nets, set the trace width in the attribute list and then provide a netlist in my fab data.
Simples.

[SiliconWizard]

EAGLE won't let you copy traces and pads without severing back annotation first, so that only leaves redrawing the pads, traces, etc., on the unused layer which is ripe for making mistakes since you don't have the benefit of using the package libraries anymore.

Oh, EAGLE..... OK!

Oh, and I thought of a real show-stopper - you can't use a stencil printer to apply the solder paste. Erf, applying paste to each pad individually - even if using a (semi-)automatic dispenser - is no fun at all.

Good point. I don't know how you could use a stencil. Or maybe it would need to be sort of embossed (stamped) where the thicker traces would lie to accomodate. The stamping may be a possibility? That would be awfully expensive though, as getting the appropriate accuracy would require a per-stencil stamping mold. Crazy.

The old way was definitely simpler. You would just not cover the traces needing extra thickness with soldermask, and then add solder to those either manually or with wave soldering. Not very accurate, but it worked.