I have many questions about USB data lane routing

[Blitzschnitzel]

Hi,
I’ve read a lot about the Dos & Don'ts of USB design. However, they all seem to focus on best practices of highspeed USB 2.0. But all I need is low speed communication for my custom keyboard design and I don’t know which parts are negligible for my purpose.

The documentation says to avoid test points, vias and T-junctions. But the area behind my USB-C receptacle is a complete salad. Is that bad?


Trace width: All the documentation assumes a 4-layer board with a ground plane underneath the differential pair. But for cost reasons I would like to use a two-layer board. (Also, JLCPCB cant do 4 layers larger than 30cm.) From the calculator I should use 0.87mm traces to get 90 ohm impedance but since the chip is the bottleneck, I can only use 0.3mm and 0.127 is the minimum distance from the manufacturer. So, I get 119 ohms. Should I make traces thicker as soon as I clear the crowded chip?


Ground planes: I have most of the data lines flanked with ground planes and a ground plane on the backside but I have to cross it with traces from the key matrix at many places. Is that a problem? I’ve made sure to only cross the data lines at an 90° angle.

Trace length: My data lanes are about 15cm long. Is that a length where it gets problematic? That's just the place where I had enough space for the chip and crystal.


Resistor placement: Some documents say to put the resistors close to the chip others have put them close to the receptacle and Texas Instruments even puts 22pF capacitors on the data lines. Is any of this really relevant?

[Solved]The Würth Electronic USB-C receptacle I want to use has two pins labelled: Centre Plate Pin
https://www.mouser.de/ProductDetail/Wurth-Elektronik/632723300011?qs=NK6InXoXhq4%252B5eM1PePLPg%3D%3D
Do I connect those to the shielding or directly to ground? I wanted to put a ferrite bead between the shielding and ground, that’s why I am asking.

[Solved]USB-C has a CC1 and CC2 pin If I get that correctly only one is used depending on cable orientation. So, can I connect them both to the same 5.1k resistor or does each need their own?

So, against better knowledge I am asking more than one question at a time in a forum.  I hope the answer is just “Don’t worry with slow speed USB.”

[Blitzschnitzel]

With a new ESD ic I was able to clean up the area around the USB port a bit:

[TimCambridge]

Simplify your life by using one of the reduced-pin USB-C connectors. e.g. 12-pin. They are standard parts, documented in the USB spec.

USB-C has a CC1 and CC2 pin If I get that correctly only one is used depending on cable orientation. So, can I connect them both to the same 5.1k resistor or does each need their own?

Don't do that! They tried that mistake in the Raspberry Pi 4 and now they are fixing it. Read the Microchip doc - AN1914 "Basic USB Type-C™ Upstream Facing Port Implementation"

[Blitzschnitzel]

Thanks for the help! I'll mark the cc1 cc2 part as solved.

They tried that mistake in the Raspberry Pi 4 and now they are fixing it.

Somewhat comforting that even the pros make the same mistakes than me.

I was super happy when I found 6 pin type c connectors but they turned out to have no data lines and were just for charging. I might end up using something like this:
https://lcsc.com/product-detail/USB-Type-C_Korean-Hroparts-Elec-TYPE-C-31-M-12_C165948.html
However, the Würth receptacle encloses the whole plug. so, I just need to put the edge of the receptacle on the edge of the case and the plug will be flush. The shorter ones almost never put in the documentation how far the plug goes in and I don't know where to place it.
This is how the keyboard is later meant to look like:

[TimCambridge]

I might end up using something like this:
https://lcsc.com/product-detail/USB-Type-C_Korean-Hroparts-Elec-TYPE-C-31-M-12_C165948.html

I used that connector on a low cost USB sniffer. To get the edge flush with the board I set the center of the front mounting pegs 2.6mm in from the edge of the board. That might be a bit too much but these tiny differences get buried in the variability when the boards are separated from a panel.

Of course a 2-layer prototype from JLC doesn't cost much and lets you verify the placements.

[edited to correct the measurement and the link]

[Blitzschnitzel]

Thank you for the advice it looks much cleaner now.

Still not sure of what comes after the receptacle though. I read somewhere that for two-layer boards you can also put a ground pour in between both data lines. Sadly, I can’t find the article anymore.

[thm_w]

(Attachment Link)
Thank you for the advice it looks much cleaner now.

Still not sure of what comes after the receptacle though. I read somewhere that for two-layer boards you can also put a ground pour in between both data lines. Sadly, I can’t find the article anymore.

Looks way better yeah. For anyone laying out the full-pin USB-C connector, it may actually be possible to not connect the alternate pins (for example B4->A4) as from what I've seen they are internally connected inside the cable. However, this may be bad practice.

No you don't want ground pour between the two data lines, you are using "edge-coupled microstrip" to layout the differential USB data lines: https://medium.com/@Altium/stripline-vs-microstrip-understanding-their-differences-and-their-pcb-routing-guidelines-9bad77303d2f

You can find a calculator to give you the trace width/spacing given your boards thickness, dielectric material, and target impedance of USB (90 ohm diff). But, 99% chance what you have laid out right now will work fine, considering this is low speed USB. Just put a nice solid ground plane below the traces, and set a reasonable clearance width rule from D+/D- to the top plane (if you have one).

CC1/CC2 should not be needed for this but feel free to implement it (likely using a USB A to C cable, so only have +5, gnd, D+, D-).

BTW I was a bit paranoid to not run traces on the top layer, because the metal shell of the USB connector will be contacting there. But for a hobbyist board, with soldermask there, I'm certain it will be fine.

[TimCambridge]

As @thm_w mentions the metal shell will hover over your top level tracks with just the resist for insulation. You can route on the top layer but you must keep close to the signal pads.

[SiliconWizard]

Looks way better yeah. For anyone laying out the full-pin USB-C connector, it may actually be possible to not connect the alternate pins (for example B4->A4) as from what I've seen they are internally connected inside the cable. However, this may be bad practice.

Probably most USB-C/USB-A cables connect them internally, although I admit I don't know. Don't know if this is required by the USB standard.

I would consider not connecting the alternate pins bad practice, same with not handling CC1/CC2 for at least one reason: your USB-C connection would not be compatible with USB-C! Which I think is bad.
Your device could be connected to a true USB-C host with a true USB-C /USB-C cable, if the two above are not properly done, it won't work. I don't think implementing an USB-C connection AND assuming it will never be used with an USB-C port is a good idea.

[thm_w]

Probably most USB-C/USB-A cables connect them internally, although I admit I don't know. Don't know if this is required by the USB standard.

I would consider not connecting the alternate pins bad practise, same with not handling CC1/CC2 for at least one reason: your USB-C connection would not be compatible with USB-C! Which I think is bad.
Your device could be connected to a true USB-C host with a true USB-C /USB-C cable, if the two above are not properly done, it won't work. I don't think implementing an USB-C connection AND assuming it will never be used with an USB-C port is a good idea.

Yeah, I see your point for CC, I would not suggest for him to remove it. I'm still curious if it would work without them populated, in some cases.

However, to connect a USB 2.0/1.1 device to a USB-C host, use of Rd[53] on the CC pins is required, as the source (host) will not supply VBUS until a connection is detected through the CC pins.

So the port should not supply power at all when idle, this is an interesting change over earlier USB versions.

[SiliconWizard]

Yeah, I see your point for CC, I would not suggest for him to remove it. I'm still curious if it would work without them populated, in some cases.

Not sure how it's implemented in practice, but from what I've understood of USB-C so far: a "host" ("DFP" in proper USB-C terms) typically detects a device ("UFP") connection from monitoring CC1/CC2 lines (that are internally pulled up to VBUS). A device is detected if either goes below a certain threshold voltage, and then a series of further identification interactions are issued. I guess if no pull-down resistor on CC1 and CC2 are present, the host will not even do anything. Just my interpretation of how USB-C works though.

[Blitzschnitzel]

Thank you all for your help! I have finally found time to redesign my board. I know now that slow speed USB isn’t that critical but I didn’t want to take chances and I have moved the IC closer to the USB-port. I also made the USB traces very thick, as suggested by the Impedance calculator. Under the data lines is an uninterrupted ground plane. The top side is also flanked with ground pour.
Now I have two questions left: How much gap should I leave between the top ground pour and the data lines? Also, now the crystal is a bit cramped at the bottom left. Is the little distance between the crystal traces and the other traces a problem? When you try to make both crystal’s traces the same length, where do you measure from? The centre of the pad or the edge?

[nctnico]

Of the cuff I'd say keep a clearance of 2 times the width of those thick traces. For thinner traces 3 to 4 times is a nice ball-park figure.

[Yansi]

Your GND routing for the ESD part is unacceptable. Place at least a via next to the GND pad. Ideally both sides of the pad.

[thm_w]

Your GND routing for the ESD part is unacceptable. Place at least a via next to the GND pad. Ideally both sides of the pad.

There is space on the top of the part (can get rid of that serpentine trace and just connect it to the other pad as you've done on the other D pin).
But I doubt there is space on the other side, via is not small enough.

Thank you all for your help! I have finally found time to redesign my board. I know now that slow speed USB isn’t that critical but I didn’t want to take chances and I have moved the IC closer to the USB-port. I also made the USB traces very thick, as suggested by the Impedance calculator. Under the data lines is an uninterrupted ground plane. The top side is also flanked with ground pour.
Now I have two questions left: How much gap should I leave between the top ground pour and the data lines? Also, now the crystal is a bit cramped at the bottom left. Is the little distance between the crystal traces and the other traces a problem? When you try to make both crystal’s traces the same length, where do you measure from? The centre of the pad or the edge?

Board looks good.
I don't see any traces near enough to crystal that would be an issue. Same with crystal trace length, its not that critical, its very good as-is. The trace running in the middle of the crystal looks really tight though, that meets minimum spacing? If not you could put a gnd via on the right side of the crystal.

Other nice to haves:
- a gnd via to the left of R8
- C5 closer to IC
- C7, C8, C9 closer to IC Vcc pins west, east, south (or on bottom side of the board, but seems like you are keeping it one sided)

[Blitzschnitzel]

Your GND routing for the ESD part is unacceptable...

Easy mate. You didn't hire me. In the last version the ESD ground went to the top ground pour and then trough a via into the bottom ground a centimetre away. What is the reason i have to make the connection as short as possible?

There is space on the top of the part (can get rid of that serpentine trace and just connect it to the other pad as you've done on the other D pin).
But I doubt there is space on the other side, via is not small enough.

OK, the serpentines were there to make the traces the same length depending on the plug orientation. The difference in trace length now only makes 2.9mm. Is that OK? I applied your suggestions as well as I could. Only, I can't put the caps on the backside and put them on all sides evenly because there are either tightly packed traces or that space will be occupied by the key switches.

[T3sl4co1l]

Don't need to leave clearance, just calculate it for the appropriate trace impedance.

You're looking for a differential coplanar waveguide calculator.  These aren't very common, but I think the Saturn PCB toolkit does it?

Tim

[thm_w]

OK, the serpentines were there to make the traces the same length depending on the plug orientation. The difference in trace length now only makes 2.9mm. Is that OK? I applied your suggestions as well as I could. Only, I can't put the caps on the backside and put them on all sides evenly because there are either tightly packed traces or that space will be occupied by the key switches.

Its OK. Nice clearance.
Maybe its just some weirdness with the graphics rendering but the ground pour under the IC looks incredibly close to some of the pins that arent GND.

Don't need to leave clearance, just calculate it for the appropriate trace impedance.
You're looking for a differential coplanar waveguide calculator.  These aren't very common, but I think the Saturn PCB toolkit does it?

Saturn doesn't have it. I wouldn't bother recalculating, leaving it as is and having the clearance is just easier at this point.

Qucs studio has it if anyone is curious:
https://electronics.stackexchange.com/questions/117214/impedance-of-an-edge-coupled-coplanar-waveguide-with-ground
http://dd6um.darc.de/QucsStudio/tline.png

[Blitzschnitzel]

Thank you all for your help. I think I can send the board to etching soon.
Here is what I am planing for the backside silk screen: