Are there any immediate reasons why this is a bad idea?
Trace width calculators out there seem to fixate on a single trace on a single layer. Can trace widths be reduced if they are routed/ganged on multiple layers? I cant seem to find such calculator or topics that may support this approach?
Are the specification values I am using as my starting point unreasonably high to start with?
I do not really have a very good intuition on safe and reasonable thermal rise /dissipation values any inputs here would be appreciated.
I am using M12-K connectors and the footprint provided by the vendor suggested "1.6mm" PCB but from what I have read about power carrying PCB I should be expecting to use 2oz or 3oz Cu so I also expected a thicker PCB. Perhaps some thoughts on stack would be appreciated also?
Trace width would be reduced by around half if the routing is on two layers, yes.
Trace calculators are quite conservative, usually use a temperature rise of only 10 C, which is minimal. But there may be other expectations like efficiency and maximum fault current that you want to think about.
1.6mm thick PCB is still no problem with 2 or 3oz copper. The thickness of the copper itself is tiny (3oz = 0.1mm).
You can use 3 or 4oz copper but it won't magically reduce required trace width to nothing. Costs will go up with more plating. eg JLCPCB goes up ~$18 if you increase 1oz to 2oz.