DEX eval by free_electron

[free_electron]

The way you should do test points is not to use vias. Setup a library component with  a square pad with solder mask relief, no solder paste, and set the component in the library to be a testpoint.

Then in the software press a button to export an Excel list of all components setup as testpoints with x, y locations (from a specified origin), the type of testpont and names.

This would be a very useful feature to go on your future todo list.

(disclaimer: I am a test engineer)

not correct.

You do NOT want to drive the testpoint from the schematic. This blocks an efficient use of available space. Depending on the tester ( some testers are top only, some are bottom only , some do both, ) and the probing technology used , you let the tool assign the test points as much as possible on existing via / pads. the tool needs to be aware of the probe to body ( given by the radius of the probe tip + an offset ) and the inter probe pitch ( given by the density of the probes and the size of the probes )

The layout software will assign as much as can be done. the ones that are 'unfittable' then get placed as free pads either on top or bottom , or additional via's are plonked down.


@iliya : the implementation you have now for via's is not flexible enough. Simply let us specify start layer and end layer. that allows for all technologies to be used.
draw such via's (that are not top to bottom ) as two half circles, one with the color of the starting layer, one with the color of the ending layer. so we visually can tell by looking at a via which layers it bridges. if it is a simple thru via simply color it grey. if it is anything but a simple : draw the two-color structure ( still a circle but one half filled with start layer colro , one half filled with end layer color , then draw the hole size over that structure.



given a 8 layer board :

if you need a simple thru-hole via : top to bottom
need a laser ? set it top to inner 1, or top to inner 2, or bottom to inner 6 or bottom to inner 5  ( 1 hop or 2 hops )
need a buried one ? inner 2 to inner 4 ( for example )
need stacked ? inner 2 to inner 3 , and a second via at same coordinates inner 4 to inner 5 )
need backdrilled ? top to inner 4 for example.

make sure the program understands layer 'pairs'.

for a 4 layer board you can only make the following bridges :
1-4 : thru
1-2 : laser
2-3 : buried
3-4 : laser

1-3 or 2 to 4 by making a 1-4 and then backdrilling

for a 6 layer board you can only make the following bridges

1-6 : normal via
1-2 : laser
2-3 : drill
4-5 : drill
2-5 : drill
5-6 : laser

the above is based on a 2 core stackup with an inner prepreg and outer lamination.

if you change this to sequential lamination then the rules change. the software needs to be aware of this. ( sequential lamination for more than 6 layers is expensive as the yield drops due to registration errors)

a 6 layer board is made as two double sided boards first ( one core each )

so you get

single layer board   layer (1)
prepreg
double sided board  layer 2 and 3
prepreg
double sided board layer 4 and 5
prepreg
single layer board layer 6

so you can drill 2 to 3  and 4 to 5 as these are each one core.

once that stack is made you can drill 2 to 5 as you have a stack of core 1 (layers 2 and 3) , prepreg , core 2 (layers 4 and 5)
so you can drill that.

then you apply prepreg and foil . now you can mechanically drill 1 to 6

you can now backdrill ( from an outer layer to any inward layer ) . note that backdrill REMOVES the plating in the hole !!! backdrilling is used in high frequency boards to remove stubs.

you can now laser from top to inner 2

this is difficult to explain in words. i need to draw a sketch how the lamination sequence works and what can be drilled when.

the rule of thumb is :

- mechanical drilling happens across cores so it is always an EVEN number of layers. you cannot drill '3' layers'.
- lasering is outer layer to 1 layer , or 2 layers below. this allows stacked / blind. they laser inner 1 before laminating the outer foil, then laser again. such holes are 'blind' : you do not see a hole in the pad as it is grown shut.

a buried via is a via that is capped : there is still a physical hole there but it is covered on both sides by pre-preg. so you can not see the copper or the hole from the outside.
a blind via is a via where you can see the copper form the outside. you do not see the hole as it is filled with copper. these are typically lasered via's.

there is a tendency in the industry to move towards laser via's more and more as it is much cheaper. Laser drills shoot almost 1000 holes a second.... on a mechanical drill that takes well over 30 minutes to do ... but  , laser drills can only go 1 or two layers ( they can only shoot 1 layer at a time , but you get two deep due to the lamination step on the outer layers , so you can shoot twice.  the reason behind this limit is the diffraction of the laser as it strikes copper. it bounces upward and destroys the prepreg.
in other words :turn on the laser , hitting copper first , then drill pre-preg until you strike copper again. the moment you get the second reflection you turn off the laser avoiding damaging the prepreg in between the copper layers.

on sequential lamination you can keep lasering as you have no 'core' apart from  the initial start in the center of the board.


again ,this is complex material and needs to be explained with a drawing.



Stacking cannot be done mechanically, only using laser

[Iliya]

The way you should do test points is not to use vias. Setup a library component with  a square pad with solder mask relief, no solder paste, and set the component in the library to be a testpoint.

Then in the software press a button to export an Excel list of all components setup as testpoints with x, y locations (from a specified origin), the type of testpont and names.

This would be a very useful feature to go on your future todo list.

(disclaimer: I am a test engineer)

not correct.

You do NOT want to drive the testpoint from the schematic. This blocks an efficient use of available space. Depending on the tester ( some testers are top only, some are bottom only , some do both, ) and the probing technology used , you let the tool assign the test points as much as possible on existing via / pads. the tool needs to be aware of the probe to body ( given by the radius of the probe tip + an offset ) and the inter probe pitch ( given by the density of the probes and the size of the probes )

The layout software will assign as much as can be done. the ones that are 'unfittable' then get placed as free pads either on top or bottom , or additional via's are plonked down.


@iliya : the implementation you have now for via's is not flexible enough. Simply let us specify start layer and end layer. that allows for all technologies to be used.
draw such via's (that are not top to bottom ) as two half circles, one with the color of the starting layer, one with the color of the ending layer. so we visually can tell by looking at a via which layers it bridges. if it is a simple thru via simply color it grey. if it is anything but a simple : draw the two-color structure ( still a circle but one half filled with start layer colro , one half filled with end layer color , then draw the hole size over that structure.



given a 8 layer board :

if you need a simple thru-hole via : top to bottom
need a laser ? set it top to inner 1, or top to inner 2, or bottom to inner 6 or bottom to inner 5  ( 1 hop or 2 hops )
need a buried one ? inner 2 to inner 4 ( for example )
need stacked ? inner 2 to inner 3 , and a second via at same coordinates inner 4 to inner 5 )
need backdrilled ? top to inner 4 for example.

make sure the program understands layer 'pairs'.

for a 4 layer board you can only make the following bridges :
1-4 : thru
1-2 : laser
2-3 : buried
3-4 : laser

1-3 or 2 to 4 by making a 1-4 and then backdrilling

for a 6 layer board you can only make the following bridges

1-6 : normal via
1-2 : laser
2-3 : drill
4-5 : drill
2-5 : drill
5-6 : laser

the above is based on a 2 core stackup with an inner prepreg and outer lamination.

if you change this to sequential lamination then the rules change. the software needs to be aware of this. ( sequential lamination for more than 6 layers is expensive as the yield drops due to registration errors)

a 6 layer board is made as two double sided boards first ( one core each )

so you get

single layer board   layer (1)
prepreg
double sided board  layer 2 and 3
prepreg
double sided board layer 4 and 5
prepreg
single layer board layer 6

so you can drill 2 to 3  and 4 to 5 as these are each one core.

once that stack is made you can drill 2 to 5 as you have a stack of core 1 (layers 2 and 3) , prepreg , core 2 (layers 4 and 5)
so you can drill that.

then you apply prepreg and foil . now you can mechanically drill 1 to 6

you can now backdrill ( from an outer layer to any inward layer ) . note that backdrill REMOVES the plating in the hole !!! backdrilling is used in high frequency boards to remove stubs.

you can now laser from top to inner 2

this is difficult to explain in words. i need to draw a sketch how the lamination sequence works and what can be drilled when.

the rule of thumb is :

- mechanical drilling happens across cores so it is always an EVEN number of layers. you cannot drill '3' layers'.
- lasering is outer layer to 1 layer , or 2 layers below. this allows stacked / blind. they laser inner 1 before laminating the outer foil, then laser again. such holes are 'blind' : you do not see a hole in the pad as it is grown shut.

a buried via is a via that is capped : there is still a physical hole there but it is covered on both sides by pre-preg. so you can not see the copper or the hole from the outside.
a blind via is a via where you can see the copper form the outside. you do not see the hole as it is filled with copper. these are typically lasered via's.

there is a tendency in the industry to move towards laser via's more and more as it is much cheaper. Laser drills shoot almost 1000 holes a second.... on a mechanical drill that takes well over 30 minutes to do ... but  , laser drills can only go 1 or two layers ( they can only shoot 1 layer at a time , but you get two deep due to the lamination step on the outer layers , so you can shoot twice.  the reason behind this limit is the diffraction of the laser as it strikes copper. it bounces upward and destroys the prepreg.
in other words :turn on the laser , hitting copper first , then drill pre-preg until you strike copper again. the moment you get the second reflection you turn off the laser avoiding damaging the prepreg in between the copper layers.

on sequential lamination you can keep lasering as you have no 'core' apart from  the initial start in the center of the board.


again ,this is complex material and needs to be explained with a drawing.



Stacking cannot be done mechanically, only using laser

Hi Vincent

I am prepared to work with you to extend DEX so it has Technology rules throughout. The user would be able to setup and switch rules for a design.
However it is best to do this offline, but keeping the forum updated. Are you up for this?

Technology rule would also include DRC.

Regards
Iliya

[Monkeh]

Hi Vincent

I am prepared to work with you to extend DEX so it has Technology rules throughout. The user would be able to setup and switch rules for a design.
However it is best to do this offline, but keeping the forum updated. Are you up for this?

Technology rule would also include DRC.

Regards
Iliya

DOES YOUR SOFTWARE take manufacturability into account? Do you have the ability to specify a stackup and control what type of via may connect to where with your optional optimization process?

Yes it does.

So much for straight answers. Carry on, nothing to see here.

[timb]

Everyone who designs PCBs for a living should really watch the video posted on the previous page. I've been designing for years and even learned a thing or two from it. (Experienced designers like Vincent et al not included.)


Sent from my Smartphone

[Iliya]

The way you should do test points is not to use vias. Setup a library component with  a square pad with solder mask relief, no solder paste, and set the component in the library to be a testpoint.

Then in the software press a button to export an Excel list of all components setup as testpoints with x, y locations (from a specified origin), the type of testpont and names.

This would be a very useful feature to go on your future todo list.

(disclaimer: I am a test engineer)

not correct.

You do NOT want to drive the testpoint from the schematic. This blocks an efficient use of available space. Depending on the tester ( some testers are top only, some are bottom only , some do both, ) and the probing technology used , you let the tool assign the test points as much as possible on existing via / pads. the tool needs to be aware of the probe to body ( given by the radius of the probe tip + an offset ) and the inter probe pitch ( given by the density of the probes and the size of the probes )

The layout software will assign as much as can be done. the ones that are 'unfittable' then get placed as free pads either on top or bottom , or additional via's are plonked down.


@iliya : the implementation you have now for via's is not flexible enough. Simply let us specify start layer and end layer. that allows for all technologies to be used.
draw such via's (that are not top to bottom ) as two half circles, one with the color of the starting layer, one with the color of the ending layer. so we visually can tell by looking at a via which layers it bridges. if it is a simple thru via simply color it grey. if it is anything but a simple : draw the two-color structure ( still a circle but one half filled with start layer colro , one half filled with end layer color , then draw the hole size over that structure.



given a 8 layer board :

if you need a simple thru-hole via : top to bottom
need a laser ? set it top to inner 1, or top to inner 2, or bottom to inner 6 or bottom to inner 5  ( 1 hop or 2 hops )
need a buried one ? inner 2 to inner 4 ( for example )
need stacked ? inner 2 to inner 3 , and a second via at same coordinates inner 4 to inner 5 )
need backdrilled ? top to inner 4 for example.

make sure the program understands layer 'pairs'.

for a 4 layer board you can only make the following bridges :
1-4 : thru
1-2 : laser
2-3 : buried
3-4 : laser

1-3 or 2 to 4 by making a 1-4 and then backdrilling

for a 6 layer board you can only make the following bridges

1-6 : normal via
1-2 : laser
2-3 : drill
4-5 : drill
2-5 : drill
5-6 : laser

the above is based on a 2 core stackup with an inner prepreg and outer lamination.

if you change this to sequential lamination then the rules change. the software needs to be aware of this. ( sequential lamination for more than 6 layers is expensive as the yield drops due to registration errors)

a 6 layer board is made as two double sided boards first ( one core each )

so you get

single layer board   layer (1)
prepreg
double sided board  layer 2 and 3
prepreg
double sided board layer 4 and 5
prepreg
single layer board layer 6

so you can drill 2 to 3  and 4 to 5 as these are each one core.

once that stack is made you can drill 2 to 5 as you have a stack of core 1 (layers 2 and 3) , prepreg , core 2 (layers 4 and 5)
so you can drill that.

then you apply prepreg and foil . now you can mechanically drill 1 to 6

you can now backdrill ( from an outer layer to any inward layer ) . note that backdrill REMOVES the plating in the hole !!! backdrilling is used in high frequency boards to remove stubs.

you can now laser from top to inner 2

this is difficult to explain in words. i need to draw a sketch how the lamination sequence works and what can be drilled when.

the rule of thumb is :

- mechanical drilling happens across cores so it is always an EVEN number of layers. you cannot drill '3' layers'.
- lasering is outer layer to 1 layer , or 2 layers below. this allows stacked / blind. they laser inner 1 before laminating the outer foil, then laser again. such holes are 'blind' : you do not see a hole in the pad as it is grown shut.

a buried via is a via that is capped : there is still a physical hole there but it is covered on both sides by pre-preg. so you can not see the copper or the hole from the outside.
a blind via is a via where you can see the copper form the outside. you do not see the hole as it is filled with copper. these are typically lasered via's.

there is a tendency in the industry to move towards laser via's more and more as it is much cheaper. Laser drills shoot almost 1000 holes a second.... on a mechanical drill that takes well over 30 minutes to do ... but  , laser drills can only go 1 or two layers ( they can only shoot 1 layer at a time , but you get two deep due to the lamination step on the outer layers , so you can shoot twice.  the reason behind this limit is the diffraction of the laser as it strikes copper. it bounces upward and destroys the prepreg.
in other words :turn on the laser , hitting copper first , then drill pre-preg until you strike copper again. the moment you get the second reflection you turn off the laser avoiding damaging the prepreg in between the copper layers.

on sequential lamination you can keep lasering as you have no 'core' apart from  the initial start in the center of the board.


again ,this is complex material and needs to be explained with a drawing.



Stacking cannot be done mechanically, only using laser

Hi Vincent

I am prepared to work with you to extend DEX so it has Technology rules throughout. The user would be able to setup and switch rules for a design.
However it is best to do this offline, but keeping the forum updated. Are you up for this?

Technology rule would also include DRC.

Regards
Iliya

Split color buried/blind vias

I can do something like this: (won’t take long)

Outer ring is top layer
Inner is the bottom layer

Red is top layer
Cyan inner
Blue is bottom

Yes, it's that 3 layer board.   
Note tooltip

[nctnico]

The way you should do test points is not to use vias. Setup a library component with  a square pad with solder mask relief, no solder paste, and set the component in the library to be a testpoint.

Then in the software press a button to export an Excel list of all components setup as testpoints with x, y locations (from a specified origin), the type of testpont and names.

This would be a very useful feature to go on your future todo list.

(disclaimer: I am a test engineer)

not correct.

You do NOT want to drive the testpoint from the schematic. This blocks an efficient use of available space.

Both methods are correct. In my design flow everything which is on the PCB (including logos) has a component on the schematic. Having to add logos, test points, etc when doing the layout isn't always the best way. Things may get lost or forgotten.

[Christopher]

I've always designed my own test jigs from scratch and added the test points into others schematics at a design for test review meeting. Adding test points to schematics as a separate component is the best way in my eyes.

[Iliya]

The very quick way to add a test point in a DEX PCB.

1. Add a pad from the Add pad menu. This automatically adds a pad inside a single pad footprint and automatically adds a schematic symbol to the first schematic.

2. To connect to it:
    In the PCB, click add net and add net by click on test pad and the dragging and click on the target. This will automatically add a wire in the schematic.
   In the schematic, add a wire.

3. Now route the net/track.

[free_electron]

I can do something like this: (won’t take long)

Outer ring is top layer
Inner is the bottom layer

Red is top layer
Cyan inner
Blue is bottom

Yes, it's that 3 layer board.   
Note tooltip

the problem is , when zooming out, these circles get small and hard to distinguish.

better to do this :

[free_electron]

on the subject of test points.

Why do so many people want ot inject these by hand. draw them in the schematic, then move them around as components. 

this is just additional work that brings nothing to the design.

Do the design, let the software analyse all via's and see which ones , using the desing rules, can be flagged as testpoints. these get marked. Nets that do cannot have one tagged automatically are listed and then the designer can inject them.

for most of the boards 90% of the testpoints are handled by the computer if you do it that way.
All the software needs to know is the minimum pitch between points.

Via;s are tented or encrooached by default, unless marked as testpoint , in which case the testpoint side is opened completely.

Any thru-hole pad or via is candidate for testpoint injection.

the software can extract coordinates automatically.

that is the way it is done  it is insanity adding symbols in the schematic for every testpoint and loading these as 'parts'  For testability every single NET needs a testpoint. so if you have a board with a 1500 pin bga you are looking at 1300 +  testpoints... good luck mucking up your schematic with all those symbols....

it is impractical and a complete waste of time doing that. the computers can handle that much more efficient. leave that to the machine.

[CatalinaWOW]

Just a couple of comments from the bottom of the food chain.

1.  While implementation of blind and buried vias is nice, it may not be an important feature in your target market (bargain, low end users).  Same with design for manufacturability.  This is again most important for high volume and/or high density board designs which may not be your market sweet spot.  You may be capable of getting DEX to the point of competitiveness for these applications, but it seems a long time before people will actually be using DEX in those places.  In my day job I was involved with some boards that had 28 layers, and many with 18 or more.  No way the people doing those are going to be using bargain software for the design.

2.  Monkeh - you are involved in a classic geek argument with Ilya.   Neither of you can win, because you both have partial truth.  But in classic geek fashion, you won't settle for partial victory.  Take the digs on design for manufacturability for example.  There was no right answer to your question.  Does DEX have design for manufacture features.  Well yes, of course it does.  There are many design rules and checks against those rules.  Does it have the specific feature you are looking for (a set of rules on placement of blind and buried vias).  I am not sure, but I suspect not at the moment.  Based on your prior posts a response of the first type would be characterized as incomplete, misleading and defensive (only one of the three is completely accurate), while the second response would have received the same type of response you gave to the indirect response - an aha, your software is defective in yet another way comment.  Same type of comments apply to passwords and other problems with the software.  I would suggest a bit of empathy.  Ilya is trying to pay the bills with a piece of software that targets a relative tiny market.  I've been there, it is tough.  When you watch your internet bill climb because of large numbers of downloads, and watch enthusiast forums comment on using your software while the revenue isn't paying the rent and food bills you have to try something.  He has tried a number of methods over the years.  I have no idea how each of his efforts has worked, though his continued efforts indicate that he has been successful enough at bringing in money, while the lack of news stories about yet another internet millionare indicate that he hasn't been wildly successful.  I suspect that he is making rather less than many or most of the pros who inhabit this forum.

[nctnico]

on the subject of test points.

Why do so many people want ot inject these by hand. draw them in the schematic, then move them around as components. 

this is just additional work that brings nothing to the design.

Do the design, let the software analyse all via's and see which ones , using the desing rules, can be flagged as testpoints. these get marked. Nets that do cannot have one tagged automatically are listed and then the designer can inject them.

That only works if the software supports that and you are using automated test beds. None of the companies I worked for used that. What remains are test points to probe certain signals. These are better put in the schematic so you can refer to the test points both on the board and the schematic from the service documentation. People need to be able to repair stuff wich is why you need test points in the schematics as well.

[IanJ]

on the subject of test points.

Why do so many people want ot inject these by hand. draw them in the schematic, then move them around as components. 

this is just additional work that brings nothing to the design.

Do the design, let the software analyse all via's and see which ones , using the desing rules, can be flagged as testpoints. these get marked. Nets that do cannot have one tagged automatically are listed and then the designer can inject them.

for most of the boards 90% of the testpoints are handled by the computer if you do it that way.
All the software needs to know is the minimum pitch between points.

Via;s are tented or encrooached by default, unless marked as testpoint , in which case the testpoint side is opened completely.

Any thru-hole pad or via is candidate for testpoint injection.

the software can extract coordinates automatically.

that is the way it is done  it is insanity adding symbols in the schematic for every testpoint and loading these as 'parts'  For testability every single NET needs a testpoint. so if you have a board with a 1500 pin bga you are looking at 1300 +  testpoints... good luck mucking up your schematic with all those symbols....

it is impractical and a complete waste of time doing that. the computers can handle that much more efficient. leave that to the machine.

I would prefer the option to use either method......with a preference for TP's to go on the schematic like a 'part' in order to keep the integrity of the design intact. IMO we have to be thinking of small, medium and large boards and what is the best way forward for each.

Ian.

[Iliya]

Test points

I believe that the use of test points can be broken down into three separate groups.

1.   Pre-part addition. Here is where you would test the board to detect errors during manufacture of the baseboard caused by misalignment of the layers etc. This is where the use of buried vias converted into blind vias would come into play.
2.   Postpartum addition. This is where you have the fully assembled board and you want to check that it works and perhaps series where Vincent’s test points may come in handy.
3.   Field service. This is where you want to test a board’s functionality when it is being deployed for a period of time in a system that suddenly fails.

From the views expressed by several people in this forum it appears that there is no one definite solution, each designer as their own thoughts. So for me, AutoTRAX should not force any specific test point strategy on users, rather it should allow several different methodologies.

I think perhaps test points could be positioned on a separate schematic with each test point being connected to an electrical node using an inter-wire connector. That would then separate out the collection of test points from the main design.

[jd]

[...]
Hi Vincent

I am prepared to work with you to extend DEX so it has Technology rules throughout. The user would be able to setup and switch rules for a design.
However it is best to do this offline, but keeping the forum updated. Are you up for this?
Technology rule would also include DRC.

Regards
Iliya

Hi Ilya, I hope you don't go off-line with it. The discussion is very interesting and illuminating.

I am learning things myself (I design PCBs as part of my job). It is interesting to see what features are
available and useful in the higher-end CAD packages.

John

[free_electron]

So for me, AutoTRAX should not force any specific test point strategy on users, rather it should allow several different methodologies.

correct.

That is how the cad tools do it. you can make a custom symbol for a testpoint and simply place and rout it as any other component.
in the layout editor there is an automated tool that verifies every net has a testpoint and runs a report showing you what is missing
there is also a tool that will, driven by rules, convert via's and thru-hole pads to testpoints automatically.

that is all that is needed to satisfy both scenario's.

a nice thing to have would be an automated tool that, for a via that is defined as testpoint, puts the net label on the silkscreen.

that is how i create labeled testpoints. let the software do the assignment , then i simply highlight the points of interest and i draw a little circle around the via and put the net name down.

[CatalinaWOW]

I actually hope this discussion continues indefinitely.  I have learned several things about DEX.  Since Iliya has not written a good manual (maybe lack of time, a hole in talent or whatever) and the bandwidth limitations of my ISP make the videos problematic this discussion has proved to be a useful training tool.  It is an adjunct to fiddling around with the software while doing whatever I am really trying to achieve.

[IconicPCB]

Ilija,

On the question of bare board testing and exposure of vias to the testing process. they are not necesary.

BBT  is concerned with end to end connectivity and net to net isolation. Gerber data, soldermask data and drill data are used in generating BBT test routines ( beyond the scope of DEX ) to detect these faults.

Grid testers are ohmic only testers where path resistance and path to path isolation are measured only.

Flying probe testers use a hybrid regime to test boards:

a) electrostatic where a data base of charge/discharge times for each net is built up to test for integrity of copper structures

b) ohmic to confirm suspected faults

DEX does not get involved in this process at all 

[nctnico]

Modern PCB fabs don't do electric testing anymore. They use a 'flatbed scanner' and scan the PCB for defects (open/short).

[IconicPCB]

That is an interesting comment.

If they are optical scanners they will not detect electrical problems.

The only contactless process I am aware of was the one patented by Jonah Systems which relies on room temperature and pressure plasma.

I have not seen anyone making this technology.

Do you have a brand name?

[nctnico]

That is an interesting comment.

If they are optical scanners they will not detect electrical problems.

In theory they could. If a trace is open or shorted to another trace you'll get a different image. But it seems Eurocircuits has gone back to electric testing. They used to have a video where they showed using a scanner to inspect PBCs. Maybe they still use it.

[CatalinaWOW]

This series of comments is probably a good caution about statements about "the industry".  There will be a wide variety of things done at various shops, with some shops still stuck on older technology, some aiming for the low price end of the market, some aiming for the high reliability end, others using technology that is best fitted to a unique major customer and so on.  If what you are doing is really important you need to find out what the shop you are using does, and understand what is important about that to you.

[IconicPCB]

In the nineties I used to operate a bare board test facility.

Arguably one of the best in the country. Had a a universal grid tester and two flying probe machines, a high speed linear motor driven bare board tester and a stepper  motor driven BBT/ MDA  tester whit incorporated a switch matrix with full 4 wire Kelvin capability on all four probes ( to be able to measure node impedances checking for Manufacturing Defects ).

The first two pieces of test equipment were at the leading edge. By the time nineties  came to the end a new BBT technology was patented. An electron beam tester was prototyped but never produced and or sold into the market at the time.

An optical scanner WILL NOT detect electrical faults with either multilayer cores or finished PCBs.

Yes it can detect mouse-bites, copper residues whihc form some of the copper faults. Finished product also tends to suffer ionic contamination, hairline faults ,  poor hole wall plating and other faults which an AOI ( automatic optical inspection ) system can not detect.

So far I have not come across traces of the promised technology of fifteen years ago ( may be the GFC and rise of Asian shops has something to do with this).

[Iliya]

a nice thing to have would be an automated tool that, for a via that is defined as testpoint, puts the net label on the silkscreen.

that is how i create labeled testpoints. let the software do the assignment , then i simply highlight the points of interest and i draw a little circle around the via and put the net name down.

What font height would you use?

[tautech]

a nice thing to have would be an automated tool that, for a via that is defined as testpoint, puts the net label on the silkscreen.

that is how i create labeled testpoints. let the software do the assignment , then i simply highlight the points of interest and i draw a little circle around the via and put the net name down.

What font height would you use?

User definable.