Dealing with high current traces with few layers

[mattmunee]

I'm building a board with multiple ASIC's in series.  Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC.  In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain.  Further, these ASIC's are connected in series, such that V- for one chip is connected to V+ for the next.  The specs for this chip say that it can draw up to 45A. 

The V+ and V- pads on this chip are 325 mils wide (150 mils tall).  In order to carry this much current from one chip to another, I'm using 4 layers of 2oz/sqft copper, with an array of vias directly in the pads.  Using PCB trace width calculators, I'm estimating that if I stretch a 325 mil wide trace/pour between the pads in all four layers, then the 2 inner layers should be able to carry approximately 9A each, while the external layers could carry approximately 18A each, for a total current capacity of 54A, assuming a maximum desired temperature change of 10 degrees C.

However, I'm trying to stick to a 4 layer board.  The design I described above means that I do not have ground planes adjacent to these traces. 

• Is that bad or very bad? 
• What are my alternatives? 
• Must I add more layers, and if so, what stack up would you recommend?
• Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current?  For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative?  I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.

Any advice you can give is appreciated.  What would your thought process be in beginning layout for such a design?  What considerations have I missed?

[thm_w]

Did you check the vias what sort of current they can carry?

Maybe some screenshots would help to visualize. As well as some sort of idea how fast this ASIC is switching. Do they have a datasheet or any instructions for decoupling it?

[mattmunee]

Did you check the vias what sort of current they can carry?

Maybe some screenshots would help to visualize. As well as some sort of idea how fast this ASIC is switching. Do they have a datasheet or any instructions for decoupling it?

Without showing too much of the design, here's a screenshot of a middle layer to show the high current trace and the vias in pad.  The via arrangement should be sufficient to get current down through the different layers, at least from a pure current-carrying-capacity perspective.  I believe the PLL of the ASIC is on the order of 1MHz, but I'm not sure how that affects the design.

[ahbushnell]

Why not make the traces wider? 

[mattmunee]

Why not make the traces wider?

As I mentioned in the original post,

Knowing that the pad itself is 325 mils wide, would it be possible to have a 325 mil trace on the top layer and a much wider trace on the bottom layer to carry the current?  For example, if I had a 325 mil trace on top (carries 18A) and a 600 mil trace on bottom (carries 28A), is that a better alternative?  I'm concerned that the vias that get the current down to the bottom layer are still confined to a 325 mil space, so I would still end up with too much heating.

Can I do that without excessive heating, knowing that the pad and hence the connection to a wider trace is only 325 mils?

[Weston]

The setup for your crypto mining ASIC is a little bit hard to visualize. Is there really no requirement for decoupling?

What calculator are you using for the trace current? Some of the calculators are based off of some standards, some have pretty arbitrarily chosen assumptions about max temperature rise. Most are assuming free standing air.

At these short lengths its less of a trace and more of just a copper pour. At these power levels the ASIC is going to be dissipating a lot of heat so I assume you have heatsinking. Any heat generated by I2R losses in the trace will end up dissipated through the heatsink.

Copper traces are not like IC interconnect where there are electromigration based current density limits, its purely a thermal problem. You should approach the problem from a thermal perspective and look at I2R loss and the thermal resistance to whatever heat sink you have. You can probably run at a higher current density than you expect.

[RedLion]

I usually spec 1mm/1A as a rule of thumb, though in automotive we tolerate much higher temperature rises. But given the length of the traces and the fact that it's on multiple layers, it sounds fine to me.

Punching holes in the ground plane is usually not an issue if you have a solid plane beneath the high frequency stuff, obviously with sufficient decoupling. Your temperature requirement intrigues me, 10°C is quite conservative. If you are worried and your bottom layer is not too populated, you can put thermal pads or even thermal adhesive on the hot bits and glue your PCB to an aluminium plate for  a crude heatsink.

Other than that I can't say much more with the information you gave.

[mattmunee]

I usually spec 1mm/1A as a rule of thumb, though in automotive we tolerate much higher temperature rises. But given the length of the traces and the fact that it's on multiple layers, it sounds fine to me.

Punching holes in the ground plane is usually not an issue if you have a solid plane beneath the high frequency stuff, obviously with sufficient decoupling. Your temperature requirement intrigues me, 10°C is quite conservative. If you are worried and your bottom layer is not too populated, you can put thermal pads or even thermal adhesive on the hot bits and glue your PCB to an aluminium plate for  a crude heatsink.

Other than that I can't say much more with the information you gave.

Thank you for the input.  I was hoping that would be the case, that ground plane is critical for high-frequency data lines and not so much power traces.  My middle two layers (except in the areas of these large traces) are ground planes for the top and bottom signal layers. So maybe I'll sleep a little easier tonight.  As for the 10°C temperature change, I'm trying to be pretty conservative, since these chips naturally generate a lot of heat on their own, and I don't want to make matters worse just through sloppy PCB design.  There will be some sort of heat sink on both sides of the board to draw away as much heat as possible.  Thanks again.

[RedLion]

I was hoping that would be the case, that ground plane is critical for high-frequency data lines and not so much power traces.

Mind you, all in good measures. A few MHz, probably ok, a few dozen, you may want to check that.
Keep the holes small and localised and apart from eachother if possible, and definitely have ground under the IC.
I assume your picture shows an edge of the IC with the bulk of it hanging over the plane.

[nctnico]

Using bus-bars is a good option when constrained for space. AFAIK you can still buy solder-in bus-bars. Maybe even surface mounted ones. Back in the TTL / ECL era, it was common to have bus-bars running acros each row of chips in high speed systems.

[eugene]

As you seem to understand already, current carrying capacity is almost purely a matter of acceptable temperature rise. In your case, you could just use the component layer for this current and add a heat sink to the PCB itself. If you're not comfortable with that, then remove the solder mask on that entire area and cover it with solder to increase the cross section. If that still bother's you, then solder down a hunk of copper instead of just adding solder. Add a heatsink and fan if you want. I wouldn't ask the board layers to carry that much current very far, no matter how many layers you have.