Well, good to hear that at least that works. However, the device is quite far from what was promised in the KS project (yeah, I know the history).
Is it? Little more than an open hardware and open firmware USB 2.0 (LS/FS/HS) analyzer was promised as far as I can tell. While the design did change quite a bit from the first shot (switched to a more modern FPGA, got rid of the XMOS which made no sense to begin with, simplified, removed a ton of feature creep), it still does buffered*, realtime USB sniffing and can be extended via unused I/Os on a .1" header. While the original had a ton of overkill stuff like a dedicated debug USB port, LCD screen, SD card slot, high-speed expansion connector, VBUS current meter, and a few other things, I don't think any of that was promised in the KS project description? Please correct me if I'm wrong. We did our best to go back to the basics and deliver something that works as promised, trying to trim things that were overkill to begin with. There's still room for quite a bit of functionality (e.g. rather complex filtering/triggering) in the FPGA, which anyone can hack on since it's open source. And, for example, even though the current meter IC is gone, there is a link you can cut to tap into the VBUS line, so you could add that as a very simple shunt+ADC module and plug it into the spare I/O port. The design is meant to be reasonably extensible.
* well, not yet, the RAM is there and well tested beyond the required speed, but not part of the USB datapath in the FPGA design yet.