pretrigger and posttrigger can almost be full scale.maybe it is shorter few sampls than full scale.
good. but i'd like to see deep memory. 4k samples is nothing. a 54620 could do that 30 years ago...
you have an 8 bit a/d convertor. how do you make 14 bits out of that ? or is there a misunderstanding somewhere.
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8 bit a/d convertor and 14 bits D/A.not the same thing.
ah, i see. what is the dac used for on the y scale ? are you using it to apply a dc offset to the input before digitizing ?
input frequency for the logic analyser 250Mhz. but the sample clock is 100Mhz ?
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The Max. input frequency is 250Mhz. the real time sample clock is 100Mhz .this is not contradiction.
ehh , you cant digitize a 250MHz signal with a 100MHz clock... especially not for a logic analyser. or are you combining input channels and interleaving them ?
also, i see a lot of these logic analyser thingies that use simply wires with grabbers at the end. no signal termination , no protection no shielded signals. kinda hard to convince me you can reliably trap signals over 100MHz.
0..5 volt input levels on the logic analyzer. what is the trigger level of the channels ? is it programmable ? ( i work on 1.2 and 1.8 volt logic. )
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Maybe you say:0V - 5V. it is not programmable. the standard is 3.3V.Maybe the logic analyzer not fit you.
ok so you use the FPGA I/O voltage . does the FPGA have embedded schmitt triggers at its input ? or do we rely on 3.3 V CMOS levels. if you use a dedicated i/o bank of the FPGA and you feed that from a programmable voltage regulator you could actually program the input levels.
screen refresh rate ? how many waveforms a second ? i don't want a machine that takes a second to refresh its screen.
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The screen refresh rate is depend on the smart device's speed and config. the max. 10fps to 100+fps is normal.
what is the dead time ? does the system keep capturing or is it frozen while refreshing the screen ?