Working with FPGA

[Stiege]

Hey everyone,

I'm recently been getting into designing stuff on an Altera DE0 board at home, but at work I'm also using a Spartan 3a-dsp 1800 development board. I'm enjoying it heaps, but I'm confused about what's required to use an FPGA without a development board. Especially regarding how the FPGA has to be reprogrammed on every power up. Are there stock parts for this? Are they unique to Altera vs Xilinx FPGAs, or is it all fairly generic.

Basically any directions on where I can read about porting my designs from the development board and onto my own board would be appreciated.

Kind regards and thanks in advance

[marshallh]

The bare minimum for an fpga design to run standalone:

1. Power supplies (I/O voltages of maybe 3.3/1.8/2.5, analog PLL supplies 2.5v, Vcore 1.2v or 1.1v)
2. Clock source (50mhz LVCMOS oscillator is common)
3. Config storage (usually SPI flash rom)

Altera's EPCS chips are just remarked ST/Numonyx flash roms. If you are careful about what specs parts you get you can find a drop-in commodity replacement.
FPGAs generally have builtin self-configuration circuitry. They have a rough internal oscillator, enough to clock in bits from the external SPI rom.
They will also have a variety of other configuration schemes, fast parallel, fast serial (QSPI), etc... It depends if you need to re-configure the FPGA on the fly to swap operating modes often, or just send updates in the field.

For lowest PLL jitter at the very least put a pi filter on the Vcca supplies, you can use a switching regulator fine.
Low-demand fpga boards can get by with just a few LDOs.

For low voltage, high current core voltages like 1v2, use a push pull converter instead of the classical buck converter. I use the semtech SC185, switching speed is 1Mhz and uses cheap small passives. For high speed switching regs like this you will want to use MLCC caps, not alum. electrolytic because of their lower ESR.

Anyway that's the real bog-standard stuff, more specific applications will come with more specific requirements.

[Stiege]

The bare minimum for an fpga design to run standalone:

1. Power supplies (I/O voltages of maybe 3.3/1.8/2.5, analog PLL supplies 2.5v, Vcore 1.2v or 1.1v)
2. Clock source (50mhz LVCMOS oscillator is common)
3. Config storage (usually SPI flash rom)

Altera's EPCS chips are just remarked ST/Numonyx flash roms. If you are careful about what specs parts you get you can find a drop-in commodity replacement.
FPGAs generally have builtin self-configuration circuitry. They have a rough internal oscillator, enough to clock in bits from the external SPI rom.
They will also have a variety of other configuration schemes, fast parallel, fast serial (QSPI), etc... It depends if you need to re-configure the FPGA on the fly to swap operating modes often, or just send updates in the field.

For lowest PLL jitter at the very least put a pi filter on the Vcca supplies, you can use a switching regulator fine.
Low-demand fpga boards can get by with just a few LDOs.

For low voltage, high current core voltages like 1v2, use a push pull converter instead of the classical buck converter. I use the semtech SC185, switching speed is 1Mhz and uses cheap small passives. For high speed switching regs like this you will want to use MLCC caps, not alum. electrolytic because of their lower ESR.

Anyway that's the real bog-standard stuff, more specific applications will come with more specific requirements.

Great!

So I'm looking for more information on the config storage. The DE0 board has a Cyclone III 3C16 FPGA. I've had a quick look though some of the literature: http://www.altera.com/literature/lit-cyc3.jsp

Is that the best way to learn about it? It talks about a lot of standards that I have pretty much no understanding of, do I have to understand all of that before I can implement a basic FPGA design? Where's a good starting point that just covers the basics for implementing an FPGA design and covers some of the options that I could look into?

[marshallh]

Read, read, read. There is no short cut. FPGAs are picky and you are only going to know what you're doing if you get in there and learn it. The Cyclone III handbook is a compilation of all relevant chapters.
Don't sweat it over all the chapters over SSTL, LVDS, QDR sram blah blah, the short story is that there are several categories of pin types and within those each pin has several different possible functions determined by the device fitter (part of synthesis)

[jucole]

A while ago I bought a very minimal fpga dev board which looks like one of these, the schematic for it is pretty much the bare essentials but it gave me a good "boost" up and over the wall into fpga land! without doing too much reading ;-)



http://www.topelectronics.com.au/image-eb/EP2C5T144.pdf

[Stiege]

That's excellent! Nice reference to Phi just there.

[EEVblog]

Just take any FPGA development board for the same chip family you are using and simply copy exactly everything it's doing. SPI FLASH boot memory, power supplies, clock, config pins etc.
Once you have that base working system, you can work backwards and figure out why they are doing what they are doing.
Different families of FPGA can have very differing requirements, let alone between brands whcih can use entirely different terminology and configuration techniques.
If you get one config pin wrong, or put the clock on the wrong pin, then your system will just sit there and do nothing, or give you lots of confusing errors.

Dave.

[Stiege]

Very pragmatic, I'll take that advice.

[EEVblog]

I forgot that I have a video on this. Kinda, it's a bit random, but might have some useful info.



Dave.

[Codemonkey]

Just take any FPGA development board for the same chip family you are using and simply copy exactly everything it's doing. SPI FLASH boot memory, power supplies, clock, config pins etc.

Not quite so straight forward with the DE0-Nano board, its also got circuitry on there that acts as an Altera Byteblaster. Its a shame you can't re-purpose it to use it to program other boards when you start doing your own designs.

[EEVblog]

Just take any FPGA development board for the same chip family you are using and simply copy exactly everything it's doing. SPI FLASH boot memory, power supplies, clock, config pins etc.

Not quite so straight forward with the DE0-Nano board, its also got circuitry on there that acts as an Altera Byteblaster. Its a shame you can't re-purpose it to use it to program other boards when you start doing your own designs.

Yes, good point. It should be a dev board that is only programmable via JTAG. Not these smarter all-in-one dev boards.

Dave.

[Neilm]

If you are looking at porting designs between chip manufacturers, do your best to ensure that the code has been done in a portable format, like VHDL or Verilog. I worked for a company many years ago that insisted that everything be done in a schematic capture format. (They used OrCad). Unfortunately for them, OrCad promptly dropped the FPGA synthesis support meaning they ended up with a station that was using an old version of OrCad and couldn't be updated and would not support the latest chips.

They then decided that the best thing to do would be using the manufacturers schematic capture options. No problem there, every thing worked - until the head office made a deal with a big FPGA manufacturer and decided that all FPGAs would be from that manufacturer.

The result was I had to re-write the code for a third time, only in this instance it was in the format I had originally asked for - having "accidentally" mentioned in a meeting that if we had made it portable in the first place, my time wouldn't have been tied up for best part of three weeks (again).

Neil

[EEVblog]

If you are looking at porting designs between chip manufacturers, do your best to ensure that the code has been done in a portable format, like VHDL or Verilog. I worked for a company many years ago that insisted that everything be done in a schematic capture format. (They used OrCad). Unfortunately for them, OrCad promptly dropped the FPGA synthesis support meaning they ended up with a station that was using an old version of OrCad and couldn't be updated and would not support the latest chips.

Out of interest, I know of cases (military) where schematic capture is used for FPGA's because VHDL ad Verilog are classed as "source code" and therefore fall under different stricter regulatory requirements. Source code in this instance has to have every line of code independently checked and verified at $$/line, but schematic capture falls under the "hardware" definition, so they get away without doing that! 

Dave.

[Marco]

It's a shame there is no universal markup for VHDL/Verilog which at least lets you (portably) design the hierarchy and signal connections in schematic form.

[Christe4nM]

Just take any FPGA development board for the same chip family you are using and simply copy exactly everything it's doing. SPI FLASH boot memory, power supplies, clock, config pins etc.

Not quite so straight forward with the DE0-Nano board, its also got circuitry on there that acts as an Altera Byteblaster. Its a shame you can't re-purpose it to use it to program other boards when you start doing your own designs.

Yes, good point. It should be a dev board that is only programmable via JTAG. Not these smarter all-in-one dev boards.

Dave.

The Terasic Max-II CPLD microkit does have an on-board USB Blaster that with a breakout header for stand alone use to program your own devices using JTAG. Unfortunately for me the shipping costs outweigh the purchase price by a lot.

[free_electron]

remarked ST/Numonyx flash roms.

No they're not. If you pay a chip maker enough he will put whatever you want on the package. No need for re-marking  . They're now made by micron. ST spun off flash to numonyx which got 'borged' by micron.

But yes, they are essentially 25F series spi flash chips. And they were fabbed by ST for a long time

[Neilm]

If you are looking at porting designs between chip manufacturers, do your best to ensure that the code has been done in a portable format, like VHDL or Verilog. I worked for a company many years ago that insisted that everything be done in a schematic capture format. (They used OrCad). Unfortunately for them, OrCad promptly dropped the FPGA synthesis support meaning they ended up with a station that was using an old version of OrCad and couldn't be updated and would not support the latest chips.

Out of interest, I know of cases (military) where schematic capture is used for FPGA's because VHDL ad Verilog are classed as "source code" and therefore fall under different stricter regulatory requirements. Source code in this instance has to have every line of code independently checked and verified at $$/line, but schematic capture falls under the "hardware" definition, so they get away without doing that! 

Dave.

It was a company making military hardware I was referring to. The diktat at the end was done from head office who also insisted we use VHDL (although after I made my comment to managers).
Neil

[Stiege]

Thanks for all that info. I have actually watched that video already, and it was very useful. I use VHDL at work on the spartan 3a-dsp, and I use verilog on the DE0. This way I'm covering all the permutations of language and brand.

Have been reading the datasheets some more and I understand the config stuff a lot better now.

Being a student is such as shame, all the will in the world but have to save my pennies to afford some of the gear I need to implement this stuff. Feel like I might try to something with a low cost Xilinx chip since I have the programmer at work. Sort of stuck with doing anything with an Altera device, as has been mentioned about the on board DE0 programmer.

[Marco]

A blaster clone is 10$.

[Stiege]

A blaster clone is 10$.

Sorry? I thought the USB blaster would be my only real option. Where could I find this clone?

[jeroen74]

A $10 clone is likely one that uses the parallel port. You don't want that.

Another one for which you don't need an external programmer:

Morph IC II. IIRC it recalls the FPGA configuration from the host PC upon connection, so might not be what you're after.

Schematic capture of FPGA logic is handy to replace old-school 74xxx based logic boards with an FPGA. You can do this with Altera Quartus and also use the special IP blocks like RAM blocks, multipliers, PLLs etc. Though replicating timing tricks with RC networks is bit trickier in an FPGA.

[EEVblog]

A $10 clone is likely one that uses the parallel port. You don't want that.

Nope, it's the USB Blaster.
AU$8.98 delivered from Hong Kong!
http://www.ebay.com.au/itm/New-Mini-Usb-Blaster-Cable-For-CPLD-FPGA-NIOS-JTAG-Altera-Programmer-/180891115065?pt=LH_DefaultDomain_0&hash=item2a1df35e39&_uhb=1#ht_4697wt_1397

Dave.

[jeroen74]

Amazing...

[Stiege]

Sweet!

[Stiege]

So just in my quest to learn more about FPGAs I decided to check out what was on the market. Found the most expensive FPGA on Mouser:

http://nz.mouser.com/ProductDetail/Altera-Corporation/5SGTMC7K2F40C2ES/?qs=sGAEpiMZZMvoScKlWpK8TBFFO0FjFVkjBsZMkmLO2aw%3d

I'm not sure who pays over $50 000 for a chip. Has anyone ever played with one of these things? What's it used for? I'm thinking maybe areas like international fibre optic link data management systems maybe?