Say a weekend project idea, something nice to build

[mawyatt]

Here's a interesting circuit from an old article that was used on the cover of the 1992 and 93 EDN yearend booklets. Origins of this circuit date back to the development of the Serrodyne Optical Phase Modulator (patent 5339055) in some of the early Fiber Optic Gyro developments.

Best,

[mawyatt]

Here's another circuit RoGeorge is familiar with, but others may not. This is a simple transistor current source with some unique properties. Was first published in EDN (or Electronics Design, can't remember) and long ago Walt Jung of Analog Devices altered alerted us to the Harrison's Book as shown.

Best, 

[mawyatt]

Here's another circuit, altho CMOS. The circuit uses a simple CMOS FF to divide the Clock by 2 but also the Vdd voltage by 2, almost exactly by 2 even with unbalanced resistors!!

The general idea, which was patented long ago (5030848) and won EDN Design Idea of the Year back somewhere in the 80s, is to use an ordinary CMOS Flip-Flop as a Voltage Divider, as well as the usual frequency divider. By using just two unmatched resistors, and a capacitor, with a CMOS FF it's possible to achieve ppm levels of precision almost independent of the resistor divider values. The resistors R1 and R2 are connected to the FF Q and Qbar outputs, and the capacitor C shunts the other resistors ends which are connected together, and called Vout. Neglecting FF timing and output characteristics Vout = Vdd(R2/(R1 +R2)), then on the next clock Vout = Vdd(R1/(R1 + R2)), C averages the result to precisely Vdd/2 independent of R1 or R2. The output characteristics of the FF have a small effect, as does the timing. If R1 and R2 are >> than the output Rp and Rn values (NMOS & PMOS Ron), then Rp and Rn have little effect, if the clock period is much longer than any FF timing skew (which causes duty cycle to slightly deviate from ideal 50%), then this has little effect. Interestingly a little circuit analysis shows the result with Rp and Rn included, Vout = (Vdd/2)( R1 + R2 +2Rn)/(R1 + R2 + Rn +Rp), thus is Rn= Rp then again Vout = Vdd/2.

This was simulated in LTspice and behaves as predicted by the circuit analysis.

Follow more details here:

https://www.eevblog.com/forum/projects/fun-circuit-to-play-with/

Best,

[RJSV]

Thanks, MK14;   That last video, (of the 4) posted here has the same 'Flicker Simulating' LED!   I've been playing around with a couple of flickering LED's with same plastic candle.
They do have a pleasing YELLOW light tone, and I figured likely a small processor on the LED die.

[temperance]

For those interested in EDN design ideas:

https://www.edn.com/design-ideas-pdf-collections-2001-2009/

The page provides links to large PDF's containing design ideas for the years 2002 till 2009.

Edit:
@ mawyatt

Here's a interesting circuit from an old article that was used on the cover of the 1992 and 93 EDN yearend booklets.

That's why I like to read EDN design ideas. Nice idea and circuit.

Ideas like this make me feel inadequate. Oh well, some people invent calculus while others are great at putting together chicken coops at an incredible speed.

[RoGeorge]

For those interested in EDN design ideas:

https://www.edn.com/design-ideas-pdf-collections-2001-2009/

The page provides links to large PDF's containing design ideas for the years 2002 till 2009.

Nice finding, thanks, added your link to this collection:
https://www.eevblog.com/forum/projects/found-a-goldmine-looking-for-more-treasures-(hp-journal-and-alike)/

[magic]

I have this simulation file dating back to 2022. I don't remember where I got the idea from, but I could swear that it was mentioned, suggested or alluded to by some IC designer, probably from National or Linear. It's supposed to be an effective way of improving differential pair linearity without paying the voltage noise penalty of degeneration resistors - SPICE says that voltage noise is the same as in an ordinary differential pair biased for the same transconductance. However, for the values shown below it takes 50% more bias current to reach the transconductance of a symmetric pair, hence current noise is 22% or 1.5dB higher.

The reason it works can be seen on the plot below. X axis is differential input voltage, green is differential output current, blue is differential transconductance. One symmetric pair has a narrow peak of transconductance near zero differential input voltage. Asymmetry shifts the peak away from zero, and two such peaks on opposite sides happily happen to create a wide band of almost flat transconductance around zero. The shallow valley in the center disappears when the ratio (N) is reduced to 3.73.

I'm sure there is lots of opportunity to tweak this further, with emitter resistors and even more paralleled pairs. The maths of it doesn't look trivial.

[mawyatt]

See post starting with #33, we were using this and the Doublet you've shown back in 80~90s, don't know where the ideas originated, but certainly was before us.

The Triplett as we've shown has the better overall linearity than the Doublet for a given input, especially 3rd order (as shown by RoGeorge), which was critical in many of our designs and why we using it more often.

The noise is the main advantage over the unbalanced emitter resistors in either the Doublet or Triplett, however at the chip level we could also get better matching with transistors than resistors, altho the Doublet offered a convenient George Erdi Cross-Couple Quad arrangement and ended up with better overall balance as could be "seen" with differential offset.

Intuitively one can visualize how the Triplett allows pushing the two unbalanced pairs further outwards wrt to differential center zero and "filling in" the middle dip of the Doublet with the 3rd balanced pair, and thus achieving better linearity within a given input span, or a wider overall span wrt to a given linearity.

Anyway, fun circuits for folks to play around with

Best,

[mawyatt]

Here's an interesting couple pages from an old notebook a couple decades ago. This is a Cherry-Hooper much simplified analysis we did to show a customer how an high dynamic range amplifier implemented in 400GHz SiGe BiCMOS achieved it's results.

These are based on "split in half" for a more simplified following, but implemented fully differential chip design. Note the implementation of "AGC" which modulated the Cherry-Hooper dual bias currents. The AGC input signal was derived from another circuit we'll try and find later.

Best,

[RoGeorge]

https://www.edn.com/design-ideas-pdf-collections-2001-2009/

Found another one that straightens the transfer function:

Diode compensates distortion in amplifier stage
S Chekcheyev, Pridnestrovye State University, Moldova
https://archive.org/details/edn-design-ideas-2008/EDN_Design_Ideas_2004_/page/n106/mode/1up



Fun trick with the diode and those cross-connected capacitors.  C3 makes the D+ of the diode to be tied to GND in AC, and together with C2, they make the diode to appear "in reverse" at AC. 

The switch is there only to step the simulation between the circuit with diode, and without (shorted diode).  When simulated, without vs with diode, the distortions went from 7% to 0.4%.

[magic]

D1 should probably be another BC547C and the whole thing seems equivalent to a differential pair - emitters connected together, D1 base AC grounded.