resistive divider -> ADC - how to get low parasitic drain?

[rr100]

I have a micro (attiny13a) monitoring a battery, I know how to save power in the micro by disabling the ADC (and putting the micro to sleep, it uses only some microamps). Question is, how to get rid of the current from the voltage divider from before ADC? I can up to a point to increase the impedance on the micro side and use higher and higher resistors. Any better idea? Mosfet controlled by the micro turning on and off the divider?

[Rerouter]

like the other thread on this topic, if your divider resistors are high enough in value, you can simple pull an output to digital low when you want to measure, for your ground,

this method will likely leave a few micro/nano-amp being drained through the protection diodes of the pin if your voltage is greater than its supply, but it shouldnt be a problem,

[digsys]

.. this method will likely leave a few micro/nano-amp being drained through the protection diodes of the pin if your voltage is greater than its supply, but it shouldnt be a problem,

He'd need to test how much leakage there was though, it may be enough to fire up the internal voltage rail.
Increasing the resistive divider MAY end up de-linearizing the ADC curve, which is not good, also to be tested.
Otherwise, you'll have to use  a NPN (transistor) - PNP (FET) pair, as you originally surmised.

[Psi]

Something like

[codeboy2k]

If you use a port pin to pull down the bottom of the resistor divider, as in the graphic, you should be aware that sleep mode on the attiny13 and maybe other attiny processors will tristate the port pins. That will put the full battery voltage into the input ADC pin during sleep. This needs to be considered, if it will damage the chip or not. Chances are no, because it will be clipped with the input protection diodes, but you will want to do the math to make sure you don't exceed the current rating of those protection diodes.

also the attiny13 is not open drain outputs, so pulling the bottom down to 0 is not really a 0. it's going to be a few mv above 0. This may or may not be a concern depending on your accuracy needs.

an alternate solution might be a P channel FET to switch the battery voltage onto the top of the divider when you wake up to read it.

[Bored@Work]

AVRs are infamous for an annoying feature. Some are very prone being reverse-powered through IO pins. I.e. if the supply power is off, but you have power on an IO pin, that voltage, via the protection diode can power the AVR or parts of it. A half running MCU is not funny, like a drunken sailor not finding his way.

So I wouldn't go with the ground-switching version, but make sure the IO is turned off externally.

[Rufus]

Any better idea? Mosfet controlled by the micro turning on and off the divider?

To eliminate drain in the divider use a P channel MOSFET to switch the top. You may also need and N channel or NPN to drive the MOSFET gate.

If you don't like the cost of those parts you are into trading off battery drain against the highest resistance divider you can live with.

Switching the divider bottom doesn't do much, the top resistor will feed into the input clamp diodes possibly causing problems and the current drain won't be much different unless the battery voltage isn't much higher than the micro supply voltage.

[rr100]

Thanks for the answers, no magic bullet it seems.
Battery voltage is 12-15V, 5V for the micro, common negative ground (but it can be changed if needed).
I need to understand how the sampling is done (I don't yet) and how much I can increase the resistors on the divider; also I need to test or maybe I can figure out from the datasheet if there's any mode in which I can put my ADC pin in some "high-impedance mode" (we're talking +0-1V on it). Then I can put a capacitor on the "output" of the divider, to slowly follow (divided) battery voltage, then when I (rarely) take a sample of the voltage I take it basically from the capacitor. Trading here bandwidth against drain.

[mikeselectricstuff]

Here's a nice solution - use a capacitor to do the level shifting
http://electricstuff.co.uk/picavrstuff.html#Measuring%20battery%20voltage

[codeboy2k]

I don't like that pnp solution with a capacitor for level shifting, there's an unknown Vbe drop
(granted, compared to the 15V battery it's negligible) but what's wrong with the PMOS solution?

It seems you are making this more complicated then it needs to be.

[Rufus]

I don't like that pnp solution with a capacitor for level shifting, there's an unknown Vbe drop
(granted, compared to the 15V battery it's negligible) but what's wrong with the PMOS solution?

There isn't a Vbe drop, there is a much smaller Vce sat drop feeding the divider.

A P MOSFET solution has an Rds on drop which is likely even smaller. What's wrong is with your PMOS solution is clamp diodes in the processor prevent IO pins rising more than one diode drop above the processor supply, including trying to power the processor through the diode. The pin will never rise high enough to turn off the MOSFET. That is why a capacitor is needed in PNP and P MOSFET solutions (if you can live with pulsed drive to the divider).

[codeboy2k]

I don't like that pnp solution with a capacitor for level shifting, there's an unknown Vbe drop
(granted, compared to the 15V battery it's negligible) but what's wrong with the PMOS solution?

There isn't a Vbe drop, there is a much smaller Vce sat drop feeding the divider.

A P MOSFET solution has an Rds on drop which is likely even smaller. What's wrong is with your PMOS solution is clamp diodes in the processor prevent IO pins rising more than one diode drop above the processor supply, including trying to power the processor through the diode. The pin will never rise high enough to turn off the MOSFET. That is why a capacitor is needed in PNP and P MOSFET solutions (if you can live with pulsed drive to the divider).

oops... my bad. I meant Vce drop. 

but still the I/O pin only has to pull down the gate of the MOSFET to turn it on.  Turning it off is done by the 10k pullup. the I/O pin can switch to tristate or become an input to turn off the gate.

finally, I see how the capacitor helps to prevent powering the device through its protection diodes.  Now I see how that's useful. OK

[Psi]

I don't like that pnp solution with a capacitor for level shifting, there's an unknown Vbe drop
(granted, compared to the 15V battery it's negligible) but what's wrong with the PMOS solution?

There isn't a Vbe drop, there is a much smaller Vce sat drop feeding the divider.

A P MOSFET solution has an Rds on drop which is likely even smaller. What's wrong is with your PMOS solution is clamp diodes in the processor prevent IO pins rising more than one diode drop above the processor supply, including trying to power the processor through the diode. The pin will never rise high enough to turn off the MOSFET. That is why a capacitor is needed in PNP and P MOSFET solutions (if you can live with pulsed drive to the divider).

oops... my bad. I meant Vce drop. 

but still the I/O pin only has to pull down the gate of the MOSFET to turn it on.  Turning it off is done by the 10k pullup. the I/O pin can switch to tristate or become an input to turn off the gate.

finally, I see how the capacitor helps to prevent powering the device through its protection diodes.  Now I see how that's useful. OK

Even when the GPIO is set to input or tristate it still cannot be pulled above mcu VCC.
So you either have 5V or 0V on the gate, which is likely to have the fet on in both states.

[codeboy2k]

Even when the GPIO is set to input or tristate it still cannot be pulled above mcu VCC.
So you either have 5V or 0V on the gate, which is likely to have the fet on in both states.

oh dammit, yeah..  I'm sleeping at the wheel on this one.

[rr100]

Very interesting discussion, who would've thought such a simple thing can be so complicated!
I finally managed to get some ADC readings and experiment a bit (that's really quick for me, I still have stuff before y2k filled under "new - to do") and it seems that input impedance is not even making a difference. Even a 220k resistor in series is doing nothing to the ADC reading (at least for 8-bit precision, which I programmed now).
Now spreadsheet says:
"The ADC is optimized for analog signals with an output impedance of approximately 10 k? or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely."
Ok, fine, higher input impedance equals slower reading. I understand the theory, how the ADC samples, etc. But numbers, how much impedance can I get if I'm willing to "wait for it"? This theoretical step I'm missing.

In practical terms probably most of my problem is stupid, I can just use high value resistors and calibrate the input (which I plan to do anyway), if the readings are consistent for the same voltage, that's the end of it.

[Rufus]

Ok, fine, higher input impedance equals slower reading. I understand the theory, how the ADC samples, etc. But numbers, how much impedance can I get if I'm willing to "wait for it"? This theoretical step I'm missing.

At speeds you need to monitor battery capacity you are limited by the errors from pin leakage current which is typically specced at +/- 1uA for CMOS processors.

100k output resistance from the divider will give 0.1v error. In practice you will likely observe much less error but have no guarantee the next chip will be as good and leakage increases rapidly with temperature.