Current coming out from the input terminal of an OPAMP?

[opa627bm]

Hi all,
I am trying to design a high speed load that can do ~50W per cell with 1000A/us

the design is pretty standard using OPA690 from TI (high driving current)

however, when I leave the input open (Driver1_IN_ALL), I measured about ~4mV acrosss RFS3. Which gives the load cell ~ 1Ａ idle current at FS_IN.

I know there is an input offset current, how come there are current coming out from the + terminal ?

also, if there is any suggestion to improve the design, will be much appreciated!

Cheers

[Zero999]

The OPA690 can have a 4mV input offset voltage and 10µA of bias current, but that's towards the worst case scenario. Are you sure it isn't oscillating? The OPA690 is a very fast op-amp for use in a constant current load application.

[opa627bm]

Hi Sir!

It is not oscillating , it will however, when I load too much (beyond 100A peak) or duty cycle is in certain range

duty : 0 ~ 1% , no oscillation, 1~1.5% oscillation, 1.5%->100% no oscillation

[Fgrir]

OPA690 Input bias current is +-3ua(typ), which across your 1.82K input resistance gives +-5.46mV.  Since the other input of the opamp has different input resistance you can't rely on the offset current spec.

[Zero999]

OPA690 Input bias current is +-3ua(typ), which across your 1.82K input resistance gives +-5.46mV.  Since the other input of the opamp has different input resistance you can't rely on the offset current spec.

This!

I got the decimal point in the wrong place when I made my previous post (I know I didn't post any numbers, but my comment was based on them).

Hi all,
I am trying to design a high speed load that can do ~50W per cell with 1000A/us

the design is pretty standard using OPA690 from TI (high driving current)

however, when I leave the input open (Driver1_IN_ALL), I measured about ~4mV acrosss RFS3. Which gives the load cell ~ 1Ａ idle current at FS_IN.

I know there is an input offset current, how come there are current coming out from the + terminal ?

also, if there is any suggestion to improve the design, will be much appreciated!

Cheers

As mentioned above, the current coming out of the input terminals is known as the bias current. The datasheet lists it as typically ±3 μA, which is being multiplied by the resistors connected to the inputs, causing an offset voltage. The resistance seen at both inputs needs to be equal, to minimise the effect of bias currents. You have 10k7||1k82 connected to the +input and 200||300 connected to the -input. Try connecting 1k43 in series with the -input.

[David Hess]

I agree with Fgrir; you are seeing the not inconsiderable offset caused by the input bias current through the input resistance.

This is off topic but I would really like to know how Texas Instruments managed to produce an operational amplifier which has input bias current cancellation *and* an input offset current which is an order of magnitude lower than the input bias current.  Input bias current cancellation should make them approximately equal.

Or is their datasheet just wrong where it says the input bias current can be positive or negative?  And of course they do not give a simplified schematic which might resolve what is going on.