How will switching times affect the deadtime setting?

[onemilimeter]

Attached is the switching time waveforms copied from the Vishay IRFP264 (N-Channel Power MOSFET) datasheet.

According to the datasheet (with an external gate resistance of 4.3ohm):
Turn-On-Delay-Time: 22ns
Rise-Time: 99ns
Turn-Off-Delay-Time: 110ns
Fall-Time: 92ns

If Deadtime is the "blanking time" configured in the DSP controller to prevent upper and lower switches in the same inverter leg to conduct simultaneously, can I estimate the "Effective-Deadtime" between the VDS of the upper switch and the VDS of the lower switch as the following:

Effective-Deadtime = Deadtime – (Turn-Off-Delay-Time + Fall-Time) + Turn-On-Delay-Time

(Assume that the gate drive circuit is perfect, i.e. no delay and rise/fall times due to optocouplers)

Cheers.

[mkissin]

Yes, that would work, but you should keep in mind that your "perfect drive circuit" doesn't exist, and that the required dead time can be increased by all sorts of other factors in the circuit.

Also, because you're presumably not driving your switches directly from your DSP, you need to take into account all of the other delays caused by both your high side and low side drivers. These delays won't be specified exactly, but the datasheet should hopefully have worst case values that you can use to build in a safety factor.