The drafting errors are more obvious and indeed understandable, after seeing the original, nut why didn't they simply copy and paste it? It's probably even the same die as the LM358, just with only one half connected.
Well, C&P won't do for updating it to whatever the latest documenting style is. Or maybe they want to have a vector or EDA version of it, who knows.
I suspect they don't have any standards as far as what schematics are drawn in, as long as they meet some minimum format and appearance standards. Possibly vector format is included in that. I've seen Altium, OrCAD, etc. in schematics, at least in the application sections / notes, so they're not picky about those at least. Probably block diagrams, inline figures, etc. are done in just, InkScape or any other variety of vector-format graphics tools. I've seen so many goofy, avoidable errors with shifted lines and inconsistent and dumb symbols, it can't be drawn with library symbols, at least it's not all the time.
Here's a particularly dumb example:
They also have a tendency (but, again, no consistency) to use the stupid emitter-arrow "MOS?" symbol, and I've seen it wired in reverse before (some LDO, don't remember offhand what). Which is exactly how
I'd think you'd wire such a bastard of a symbol, but nah, the convention is apparently analogous to an NPN and the "emitter" is supposed to be the source.
And as you can see above, sometimes they draw an insulated gate, sometimes not. Hm, don't think I've seen -- wait wait wait hold up I've got another one.
https://www.ti.com/lit/ds/symlink/ucc256304.pdfThe HV startup circuit, they consistently(!) refer to, throughout the datasheet (and its relative the -404), as using a "JFET". These are CMOS chips. There's no fukkin' way they put an HV JFET in there. The block diagram shows a MOSFET, as you'd expect. Is the block diagram actually lying then?
Anyway, I was going to say, while they've sometimes removed the gate oxide, I don't think I've seen a gate
junction (arrow to/from substrate, i.e. a JFET) before, just, at the simplest, the IC version of symbol (symmetrical D/S, SS left off, gate circle/not indicates P/N channel). Without it actually being a JFET, I mean (and at that, mainly just among the classic op-amps; very little indeed uses JFETs anymore? at least on block level).
Tim