How does doping go with the nanometer scale?

[VinzC]

Hi all.

Maybe this question was partly answered in this board but I'm still curious as I haven't found the answer yet — probably out of laziness, I kindly plead guilty.

How do industries do doping if — correct me if I'm wrong — P or N doping is a matter of proportions such as 1 atom in 100,000 (strong doping) or 1 in 1,000,000 (normal doping)? How does that go with high integration scales where layers are made of only a few atoms?

Thanks in advance for your highlights.

[Nominal Animal]

Consider this: in crystal silicon, the distance between nearest neighbors is 0.222 nanometers (0.222 nm = 2.22 Å = 222 pm).

The term "5 nm process" does not mean the features are on that size scale, it's just a label.  It is better to look at transistor densities.  One square millimeter is 1,000,000,000,000 square nanometers, and each square nanometer has about 6.78 silicon atoms on the surface of crystal silicon (FCC, or face-centered cubic lattice).

If we look at known transistor densities, let's consider the CLN5FF 5nm process by TSMC in 2019: 171,300,000 transistors per square millimeter.  In surface area, we're therefore talking about 39580 surface atoms per transistor, or about 140×140 cells of the FCC lattice (which has an atom at each corner of a square face, and one in the center of that face, so two atoms per cell, on the surface of the lattice).  That count only applies to the surface area, mind you; the structures also have depth, possibly hundreds of atoms deep, and at these scales we really need to look at the quantum mechanical model of the electron densities (a few outermost electrons only really interact, though), and cannot rely on macroscale rules of thumb like "current flows on the outer surface" at all.

The purpose of doping is to introduce vacancies (P-type, using acceptor dopants) or extra electrons (N-type, using donor dopants), and at these proportions, not to change the lattice properties otherwise.

Because we are very well within the quantum realm at these scales, the doped atoms do not really stand out that much from the lattice.  (Actually, they do; the way they distort the lattice around them, depending on their own electron structure, is kind of a problem.  But the reason for the doping, the extra electron, or the lack of an electron at that position in the lattice, really is "spread" pretty evenly over a large volume, not localized to that spot like one might think if they mentally visualize atoms as marbles or similar things.  They're not, not at this scale.) In a very real sense, instead of that extra electron or electron vacancy being localized there, it really is shared within the lattice.  If there was no distortion in the lattice otherwise, it would not matter much exactly where the dopants are, as long as they are not clustered together and were evenly distributed.

What does this mean, then?

It means that at this scale, we cannot design circuits like we do e.g. PCBs; it is more like building with LEGOs, and designing each LEGO (say, a FET, or a small high frequency conductor) using simulators modeling the actual electron-electron interactions using quantum mechanical models.  These take a LOT of computing power to verify, especially because you really want to know if the block properties change depending on the doped atom location et cetera... but at the base of it, they are just invented by us humans, and then found via simulation and experiment to work well.  The models – like how exactly is a FinFET constructed on a wafer – are well known in literature, but as far as I know, the exact practical details are Dark Magic Trade Secrets, known by all competitors, but not openly talked about.

The transistors are obviously the main building block – or at least the functional one –, but even "connecting wires" are similar building blocks at this scale.  You don't just draw them willy-nilly as you like; they and their interaction with the other building blocks must be modeled and known.  Essentially, nothing is "passive" at this scale.  It has been this way for a few years now already.  By shrinking the blocks, we need more functional blocks, and model them even more precisely, as the smaller scale will mean that only specific types of blocks will work together.  For example, instead of a single FinFET "block" you use everywhere, you need a few different variants depending on what is around it and so on, and use the appropriate one for each – even though logically it is always the same "block".  So, real-world engineering and physics work, to find out what works, both via simulation and practical experiments on wafers.  Whether you consider that scientific or engineering research I can't say; to me, it's one and the same (and includes quantum chemistry, too) at this scale.

I myself am a molecular dynamics or computational materials physics toolmaker, trying to provide a next generation simulator for similar stuff – except that I don't work with the quantum mechanical models, but "classical" potential/force-field models, for examining non-electrical physical properties, like corrosion/radiation resistance and similar material properties.  (Right now, all simulators really use programming techniques from the 1970s, and basically everybody is just throwing more hardware together to get shit done, instead of making the simulator software work better with the hardware we have. I'm that sort of a toolmaker: grumpy and unhappy about the waste of potential.) So, I have not done any of the kinds of simulations needed above myself, but I have supported users doing exactly that on VASP, Dalton, Gromacs, LAMMPS and other simulators; but even as a "glorified" programmer, my own core field is a bit different, on simulating the material properties in slightly larger systems (tens of thousands to billions of atoms – still less than a cubic millimeter of material –, but including things like how the doping process itself can be done, what is the penetration depth, damage to the crystalline structure, and so on).

Which means that if anyone with actual practical experience cares to post in this thread, that does trump my "theoretical"/simulation-based knowledge.

[T3sl4co1l]

To add to that sense of scale in the stack-of-balls model -- an electron isn't pointlike, but rather smooshed out across, hundreds of atomic radii I think, depending on energy (wavenumber, whatever).  Electrons in a crystal behave exactly like electromagnetic waves in a metamaterial, specifically a 3D lattice waveguide.

We even observe the same effects in an analogous EM structure: a transmission line or waveguide with periodic perturbations (alternating high and low impedance sections) gives a bandstop characteristic -- an electromagnetic bandgap (EBG).  That is, EM waves are prohibited at certain wavelengths.  So too, in a crystal, electrons are prohibited at certain wavenumbers.

And just as an EM wave is not a particle but the entirety of the field in the structure, so too, the electron is a field throughout the crystal.  We identify particle-like properties under certain conditions, but those do not so much apply here.

So it's quite possible that charge carriers, thermally generated by the dopant atoms, wiggle about within the structure, making their presence felt pretty much wherever within the transistor.

Actually, we're at such small scales that, I think Debye shielding and thermal drift aren't very meaningful anymore?  That is, below the mean free path of an electron bouncing around such a small bit of silicon*.  Although maybe that isn't a meaningful point, as Debye length depends on doping (which is relatively strong here), and thermal drift may simply find charge carriers diffuse into (effectively, short circuited into -- recombined at) the connection terminals, in which case the concentration is simply the production rate from the dopants versus the sink rate by the terminals.

*And note that these are small discrete bits of silicon, indeed -- transistors are constructed on a die, then cut off from it using SOI (silicon on insulator) techniques.  Usually something like, burying oxygen ions at a certain depth into the crystal, then annealing to form a buried layer of SiO2, insulating the transistors from the substrate.  Which means the transistors are no longer metallurgically part of the same crystal, they still have the same orientation but do not touch it anymore.


On a tangential note, I wonder how many atoms of dopant are needed, before they precipitate as other compounds, out of such a tiny bit of silicon crystal?

Tim

[David Hess]

How does that go with high integration scales where layers are made of only a few atoms?

As your question alludes to, poorly.  The discrete nature of doping means that variation of the doping becomes greater as fewer atoms are involved.  This creates an ultimate limit on feature size.  As you might expect, compound semiconductors reach this limit earlier.

[VinzC]

Well, thanks a lot for your elaborated response, guys. Just not sure I understand my own question now...

Maybe I should have narrowed it down to what I wanted to know exactly: a) are the advertised ratios — 1 in 1E5 for strong doping and 1 in 1E6 for normal doping — correct and b) are those ratios (roughly) conserved in high scale integration?

From what I've read above (thks Nominal Animal) that would be more like 1 "impurity" in 10,000 atoms minimum, right? So if that ratio makes sense, that's more than 2 orders of magnitude above normal doping, right? And we're only talking about the smallest "concentration", still with me?

So if the smallest "impurity" concentration is 100 times that of a normal doping, what's a strong doping like P+ or N+ then? Does that makes sense? Or is it the ratio between concentrations that matters? (I mean as long as strong doping is 10 times that of normal doping is okay... does that reasoning make sense?)

[Nominal Animal]

are the advertised ratios — 1 in 1E5 for strong doping and 1 in 1E6 for normal doping — correct

No idea; those are the practical details I don't personally know.

are those ratios (roughly) conserved in high scale integration?

Even at the current 5nm fabrication processes, we're already in the individual atom scale, basically.  A single FinFET at the fabrication process I mentioned consists of something like a few dozen million atoms.  Any rule of thumb (as in an extra acceptor or donor in 100,000 or 1,000,000) just does not apply.

If you look at a FinFET, it is a structure with a lightly p-doped substrate, and a heavily n-doped gate, with oxide-based insulator (surface oxygen binding generates a nice insulator layer), plus a few deposition tricks to help with the manufacturing.

The base substrate is manufactured in bulk, and is large: a continuous "block".  The fins of FinFETs are created by etching (and mechanically polishing) this material.  However, because the bulk substrate is continuous with the exception of these fin structures (after etching), the fin structures' semiconductor properties are the same as in the bulk.  This is because the effect of the acceptor atoms is not local in continuous bulk.  If the substrate was only a thin layer, or it was cut up into smaller blocks, then the situation would be completely different.  (In other words, you don't need any acceptors in the fin structures themselves.  I suspect, but have no proof, that one of the Black Magic Trade Secrets is that the acceptors are actually distributed at specific depths, with none at the etched surface, so that the fin structures are always just pure silicon, relying on the effect of the acceptors in nearby bulk material below.)

The FinFET gates are small blocks of heavily n-doped (with donor atoms) polycrystalline silicon.  These are deposited (or "grown") to the surface.  Polycrystalline means it is not a single lattice, but consists of "grains" of similar lattices but at different orientations.  My understanding is that each grain basically contains single donor on average; that the grain boundaries keep the structure stable at room temperatures stopping the donors from diffusing around too much, but is basically the only way we can reliably grow doped semiconductors at these very small scales.

The suggested steps beyond FinFET that I've seen, includes things like nanowires replacing the fin structure.  Problems there include things like how to position them; using an atomic force microscope to place each one is just ridiculously un-feasible, like asking someone to build a concrete skyscraper but inspect each grain of sand separately...

Okay, so what does this mean with regard to semiconductor doping?

You cannot dope small structures.  You need bulk.  Fortunately, the effects of the acceptors and donors reaches a large volume in uniform bulk.  (If you consider a face-centric cubic lattice with 1:100,000 doping, the average distance between neighboring dopants is about 23 lattice cells; 50 for 1:1,000,000 doping.) So, you can have small features protruding from or etched into the bulk, and even if they don't contain any acceptors or donors themselves, they still exhibit basically the same semiconductor properties as the bulk does.  Our manufacturing is already at this scale, and this works just fine.

For small pieces like the gates on FinFETs, we don't have bulk. Polycrystalline silicon isn't continuous; it really is like grains.  The grain boundaries have properties that need to be accounted for; in many ways, they can be treated as nanocrystals.  Fortunately, we have techniques for growing darn uniform nanocrystals already, so that's not a problem.  But, can you really call the gate an uniform structure?  Yeah, because the range of properties that Just Work is pretty wide.  If you take an electron microscope, the individual transistors aren't "clean", there's all sorts of warts and dents in them, and they still work fine.  So, someone working at the transistor level, say designing an IC, doesn't need to worry about that.  But when actually designing a new gate, a model with uniform gate structure is not very realistic; you cannot just consider it "some heavily n-doped silicon or germanium here".

The manufacturing methods we have also means we cannot design at the atom level.  It really is more like growing plants from tiny seeds you need to throw handful or more at a time.  You can control their density, the amount of nutrients and water and light they get, but not exactly where each individual plant is.
This means that we really cannot use doped semiconductors for tiny structures; we need to use something else.

If we want to manufacture even smaller individual structures (not etched into or protruding from bulk), we'll need something else besides doped semiconductors.

Polycrystalline materials is my bet, used somewhat like nanocrystals as building blocks; and packing more functionality inside a single few-tens-of-nanometers "unit block" volume, for example by combining different types of transistors and maybe even optical components into a single "unit". Perhaps a set of nanodots can be used to generate small amounts of light to excite surface effects in the transistor structure, so we'll have a single-component electro-optical logic gates.  Even now, FinFET structures already have multiple fins to increase current capability; perhaps that feature could be used to implement multi-level logic at the transistor level.  Or perhaps we'll find a way to get rid of the waste heat, and just start packing multiple layers of FinFETs on the wafers.

I must say that I'm getting uncertain whether I should have posted in this thread at all.  I don't know the level of knowledge of those who are reading this thread, and my attempt of trying to explain it in layman terms without going too much into technical details and jargon (only enough to make it easier to find further reading by looking at the keywords), may have backfired, leading others astray.  Plus, I'm often wrong.  So, if anyone thinks I've made an error here, let me know.  If you don't want to do it publically or aren't sure if it's an error, just drop me a PM or an email; I'd appreciate it.  I'd hate to have misled anyone in their pursuit of understanding!

[T3sl4co1l]

The base substrate is manufactured in bulk, and is large: a continuous "block".  The fins of FinFETs are created by etching (and mechanically polishing) this material.  However, because the bulk substrate is continuous with the exception of these fin structures (after etching), the fin structures' semiconductor properties are the same as in the bulk.  This is because the effect of the acceptor atoms is not local in continuous bulk.

Wait, so FinFETs aren't SOI?

I had just always assumed they were... but that makes sense.

I see a few references for SOI FinFETs, but not obvious if that's just reporting from the time, or used in current tech or what.

Polycrystalline materials is my bet, used somewhat like nanocrystals as building blocks; and packing more functionality inside a single few-tens-of-nanometers "unit block" volume, for example by combining different types of transistors and maybe even optical components into a single "unit". Perhaps a set of nanodots can be used to generate small amounts of light to excite surface effects in the transistor structure, so we'll have a single-component electro-optical logic gates.

How big is a typical poly-Si crystallite anyway?  10s nm?  Up to ~cm of course, like for solar cells.  Does one of those transistors even have more than one crystal orientation in its gate?  Maybe a few is possible, I guess.

Using them for transistors, as well as optical components, would certainly be interesting...

Tim

[Nominal Animal]

The base substrate is manufactured in bulk, and is large: a continuous "block".  The fins of FinFETs are created by etching (and mechanically polishing) this material.  However, because the bulk substrate is continuous with the exception of these fin structures (after etching), the fin structures' semiconductor properties are the same as in the bulk.  This is because the effect of the acceptor atoms is not local in continuous bulk.

Wait, so FinFETs aren't SOI?

Both silicon-on-insulator and bulk FinFETs do exist, see e.g. here for a comparison.  However, in the smallest currently used scale, the source-drain "fin" has to be connected to bulk material, to be lightly doped silicon: there just aren't enough atoms to achieve "lightly doped silicon" properties with such a small volume of silicon.

That does not mean it is impossible to construct a small area FinFET on top of an insulator; you just then need a large block of same bulk material next to the fin – or you need the small-volume details like the fin to be pure (mono- or poly-)crystalline lattices, not doped material.

Our existing tech is surprisingly good at "growing" just a few atom thick uniform layers, as long as the lattice structures are compatible enough (similar lattice constant, so they can "lay flat" against each other).

Some of the nanotube research, I think – but have absolutely zero proof, so consider this just a hunch – could reveal ways how layered materials, consisting of just a few layers of each element, like a sandwich – have suitable properties to be used with FinFET or similar transistor structures, replacing doped semiconductor materials.  That could allow another scale factor of ten in width or height, so maybe a 100× density increase, if one could just discover one that works with current fabrication methods, since it drops the necessity for "doped" semiconductors.  Layered structures are how the wafers are created now anyway.  (Nanotubes with analogous structures have shown real interesting properties, including superconductors, you see.)

How big is a typical poly-Si crystallite anyway?

You can control it.  Basically, you can grow the Si nanocrystals in vacuum.  By controlling the exposure time, temperature and pressure (and optionally with the help of an inert gas), you can control their size very precisely; they will be surprisingly uniform in size. Then, the nanocrystals are implanted on the desired surface.

There are also ways to grow the polycrystalline structures directly on the surface, but since the polycrystalline material used in FinFETs is heavily doped, I believe growing the nanocrystals around the donor atoms, and having the nanocrystals deposited to the surface as a separate step, is the most scalable method to do this in actual manufacturing.

The interesting thing is that the boundary layer – surface in nanocrystals, lattice boundaries in polycrystalline lattices – itself behaves completely differently to the bulk material.  Instead of changing the elementary atoms, you only need to control the crystal size, and you can control its properties!  Back in 2005, researchers at California Instutute of Technology created a transistor using pure silicon, just by embedding nanocrystals in conventional bulk silicon. They used 2-4nm diameter Si nanocrystals.  Even smaller Si nanocrystals might still have useful properties, but I assume this 2-4nm is likely, as it produces the desired properties for the nanocrystals/grains.

Using them for transistors, as well as optical components, would certainly be interesting...

For sure.  Nanocrystals (nanodots) are used in LEDs already, including silicon nanocrystals; we already know they "work".  Manufacturing them isn't too expensive either.

I don't really see the progress being in shrinking the individual building block, beyond say that 100× increase in surface density.  Even that may be impossible due to thermal issues.  What I think will happen, is the building blocks will become more complex, so that instead of structures implementing a single transistor, we pack much more functionality in each block, and use a number of different such blocks on each wafer to realize the structures.  The complexity goes through the roof, though.  While the substrate and manufacturing process will surely include doped semiconductors, I think structured materials (nanocrystals/polycrystalline materials, tubes, layer structures) will be the key.

There are also some very interesting completely different approaches, like spintronics and spin-wave logic gates, based on magnetic effects.  The name comes from electron spin, a quantum mechanical property in certain ways analogous to angular momentum, which can be manipulated via magnetic interactions at the atomic or single-electron level.

[VinzC]

I must say that I'm getting uncertain whether I should have posted in this thread at all.  I don't know the level of knowledge of those who are reading this thread, and my attempt of trying to explain it in layman terms without going too much into technical details and jargon (only enough to make it easier to find further reading by looking at the keywords), may have backfired, leading others astray.  Plus, I'm often wrong.  So, if anyone thinks I've made an error here, let me know.  If you don't want to do it publically or aren't sure if it's an error, just drop me a PM or an email; I'd appreciate it.  I'd hate to have misled anyone in their pursuit of understanding!

Well, you clearly went way beyond what I expected as an answer but, okay, I asked how it's done and you've shared your knowledge on the matter. I'm still interested in knowing (the orders of magnitude) the doping concentrations in high scale integrated circuits, for my own curiosity but also because it's a ratio I tell my students. It is too unfortunate that the sources I viewed do not themselves source their numbers. It's not the only time I see/hear doping ratios about 1/1E6 or 1/1E5 but I'd have liked to know where they come from, if the industries ever share them publicly. It's hard to find, at least with my (veeeeery) limited knowledge in the field.

That said you've narrowed my searches a little bit explaining the concentration ratios I talked about are (more or less) feasible, just not applicable to a planar model (is that the appropriate term?) at those ridiculously small scales but to a 3D model, which makes sense to me. Fair enough, so.

[T3sl4co1l]

You see doping concentrations in n/cm^3 more often.  With 1e15 being pretty common (in general; these will be a few decades higher concentration), compared to say 1e23 or so being comparable to the number of atoms in a unit volume (~Avogadro's number).

Tim

[Nominal Animal]

I'm still interested in knowing (the orders of magnitude) the doping concentrations in high scale integrated circuits, for my own curiosity but also because it's a ratio I tell my students. It is too unfortunate that the sources I viewed do not themselves source their numbers.

That is, I believe, because this number (of dopant atoms per bulk atom) is so variable, and actual the dopant density (typically in atoms per cubic centimeter) is easier to refer to in practice, just like T3sl4co1l mentioned above.

If you look at the math (density of states, or even just number of charge carriers in different temperatures), depending on the bulk atoms and the acceptor/donor atoms, the change in properties varies wildly.  Instead of referring to the fraction of atoms, materials physicists at least are actually referring to how strongly the doping changes the bulk properties; and depending on the elements in question, that may change the "limit ratios" by several orders of magnitude.  The actual dopant density (number per cubic centimeter) is "just a technical detail".

If you look at e.g. the Wikipedia Doping article, it says "When on the order of one dopant atom is added per 100 million atoms, the doping is said to be low or light. When many more dopant atoms are added, on the order of one per ten thousand atoms, the doping is referred to as high or heavy."  However, it has no references to that claim; it just shows that we're talking about BIG differences, and even at very high or heavy doping, the dopants are still "rare".

The Wikipedia semiconductor article mentions that doping pure germanium with arsenic at 1:100,000 increases the electrical conductivity by a factor of 10,000.  I'd call that heavy doping, even though it is one tenth of what the other article calls "heavy doping".

If you were to ask for my opinion, I'd say 1:100,000 or more is heavy doping, and 1:10,000,000 or less is light doping, and amounts in between can be either depending on the atom elements involved, because doping is such a sensitive matter.  (Oh, darn, that's a physicist dad joke. Sorry.)

just not applicable to a planar model (is that the appropriate term?) at those ridiculously small scales but to a 3D model, which makes sense to me.

Yes to both.

Put simply, in continuous volume, the effects of a single dopant reaches tens to hundreds of lattice cells in each direction (depending on the lattice atoms and dopant atoms). Both Si and Ge have FCC lattices, with lattice sizes (lattice constant, "edge length") 0.543nm and 0.566nm, respectively; so we're talking about nanometers to tens of nanometers in silicon and germanium semiconductors.  Any kind of barrier, be it discontinuity in the lattice structure (grain boundary in polycrystalline silicon, or other defect) will "block" it, however; and the exact electron densities in any particular structure needs quantum mechanics to be modelled properly (and such software exists, e.g VASP, Dalton, Siesta, Turbomole) because the results are not intuitive or similar to physical objects in macro scale; and those simulations are slow.

So, we can do very small features in 2D, if we keep the size in the third dimension large enough to have the necessary continuous volume.  FinFETs are, for just this reason, called non-planar or 3D transistor.

(A student might point out that wouldn't the fin in a FinFET act like it was less doped than the bulk it was etched on – because obviously the effect must wane as distances increase –, to which the answer is "yes, of course; but the range of semiconductor properties where such features work is wide enough".)

To get much smaller – that is, closer to the single-atom transistor limit, which we already know is at least theoretically possible with spintronics but basically merges classical logic gates and quantum computing –, we need to switch to using non-doped semiconductors for the small-volume details.  Because surface or grain boundary has completely different properties than bulk material, we can use polycrystalline material in similar ways to doping: the grain size dictates the properties.  Other possibilities currently being researched involves nanowires, nanotubes and layered structures; the layered structures being the cheapest, but nanowires and nanotubes being hyped the most.

[VinzC]

[...] doping is such a sensitive matter.  (Oh, darn, that's a physicist dad joke. Sorry.)