An excellent illustration on how DRAM works.

[BrianHG]

Here you go, I skipped the over bloated intro:

https://youtu.be/7J7X7aZvMXQ?t=490

Sadly, there are 2 tiny marketing segments, but the internal silicon structure and it's functional layout and explanation is worth it for those who want to know even just the ingenious means of canceling noise on the silicon across the rows and columns, meaning you need to watch the whole thing.

[BrianHG]

From watching the video, I now know why my DDR3 ram controller with VGA display driver in the FPGA thread powers up to a noisy, but visual distinct checkerboard black and write pattern when I set the horizontal resolution to a large enough 2^x width.

It's the design of differential sense row buffers used to cancel out the effect of adjacent trace capacitance in the columns of the ram chip.  Powering up means each adjacent row is glitch - charged high, next low, next high, next low as these sense amplifiers are turned on for the first time.

[pcprogrammer]

Yep, for those interested in this kind of things certainly worth watching.