A DC power supply for 16-bit ADC

[onemilimeter]

I wish to design a DAQ board with a 16-bit ADC and an input analog span of +/-5V.

Thus, the resolution is 10/(2^16)=0.000153=0.153mV.

In my opinion, the noise of the DC supply to the DAQ board may affect the effective resolution of the ADC.

Kindly share your view and opinion on how to design a DC supply for high resolution ADC circuit.

Thanks.

[DaveW]

Have you considered using a separate voltage source for the ADC, a voltage reference chip can supply a small amount of current to a very high precision, +-2mv and under 10ppm temperature drift can be bought off the shelf? You can also use this to reduce the effect of the rest of the circuit on the voltage supply. Are you putting the input signal through any circuitry before it is fed into the ADC?

[mikeselectricstuff]

Most ADC manufacturers have plenty of appnotes on how to get the best performance - take a read through these to get a n idea of what's required

[Simon]

the simplest method might be to power the MCU with a linear reg like a 78L05, or as others say use a voltage ref if you need high acuracy

[slburris]

There are voltage regulators designed to have very low noise,
for RF and precision analog applications.

I'm not much of an analog guy, so you probably want to read
through the datasheets yourself :-)

For example, National's LP3999 is an RF regulator with 10uV of noise:

http://www.national.com/mpf/LP/LP3999.html#Overview

Maxim has an app note about reducing noise to 7nV:

http://www.maxim-ic.com/app-notes/index.mvp/id/3656

and finally Wenzel has a number of interesting noise cleanup
circuits:

http://www.wenzel.com/documents/finesse.html

This might be overkill for a 16bit ADC though.

Scott

[CafeLogic]

I just dealt with that actually.

http://www.cafelogic.com/articles-2/a-reflow-controller-for-soldering-with-a-griddle-or-toaster/

See schematic/layout for analog module.

I had no trouble getting full 16-bit on input of +/- 16mV so 5V should be a piece of cake (depending on output impedance).

Bottom line is think about how your digital currents are going to return to the source and if they are going to return through your analog components. Remember that currents do not return in one piece meaning a portion will always flow through the analog section. The point being that if the digital return path is twice as good (1/2 the impedance), you'll still have 33% flow back through the analog.

Don't run high speed traces across breaks in your ground plane. If you don't have a power plane, use traces at least three time fatter than normal for your power and consider using a separate linear regulator to power the analog.

If you don't have a ground plane, you are going to have a hard to time achieving 16-bit.

For the power-noise, use an external precision reference with good PSRR.

Last thing, consider the bandwidth you need and construct an RC filter at the input of your ADC that filters out higher frequency.

Oh yeah, big ass low-esr bypass caps on all ICs.

[tyblu]

There are voltage regulators designed to have very low noise,
for RF and precision analog applications.

I'm not much of an analog guy, so you probably want to read
through the datasheets yourself :-)

For example, National's LP3999 is an RF regulator with 10uV of noise:

http://www.national.com/mpf/LP/LP3999.html#Overview

Maxim has an app note about reducing noise to 7nV:

http://www.maxim-ic.com/app-notes/index.mvp/id/3656

and finally Wenzel has a number of interesting noise cleanup
circuits:

http://www.wenzel.com/documents/finesse.html

This might be overkill for a 16bit ADC though.

Scott

Great links, Scott! (Great Scott, links!) I love app notes like these -- better than any textbook.

[CafeLogic]

I'm not much of an analog guy, so you probably want to read
through the datasheets yourself :-)

I bookmarked these, thanks.

[jahonen]

Walter Jung's bootstrapped "super" regulator is even better, but has some limitations.

Regards,
Janne

[jahonen]

Another thing to consider is that low-data rate sigma delta ADC's are much easier to get 16 or more bits, since they naturally reject multiples of AC mains harmonics, if the data rate (modulator clock frequency) is suitably chosen. If one needs to sample much higher rate, then the job gets much harder, as there is no natural rejection of line noise.

Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning bet

Regards,
Janne

[CafeLogic]

Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning bet

This was a point of confusion for me because there are 100 papers that say do and 100 papers that say don't. It seems like there are some major themes agreed upon, like if you do, then don't run high-speed traces across the gap. One microchip note even said do for delta-sig but don't for SAR. I haven't read the one you referenced (that I can rmember) but I will when I have time. Generally, I have found that the EMC people are the ones that usually screen don't, not sure why. My normal method of dealing with conflicting information in any science is to accept the info with the best supporting evidence. I happen to like this paper:

http://www.nxp.com/documents/application_note/AN10974.pdf

I am not going to pretend to have all the answers on that one.

[CafeLogic]

Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB.

I actually have read this paper, it was one of the good ones I thought.

[tweek]

http://www.cafelogic.com/articles-2/a-reflow-controller-for-soldering-with-a-griddle-or-toaster/

A bit off topic but that is a sweet controller.  That display is really nice.

[RayJones]

You have not stated the sampling rate you are using?

If using a high sample rate, you may also wish to ensure the clock used for sampling is also ultra stable. This may require a separate supply just for the clock generator.

The best way to evaluate you noise performance is to capture 2^n samples eg 1024. then perform an FFT on the results.
This will reveal if you have any spurious signals getting in there, degrading performance.
Even better to reveal spurious signals is to average multiple FFT's over time.

Simply seeing one digit of noise is not always indicative of a good sampler. 

[onemilimeter]

You have not stated the sampling rate you are using?

If using a high sample rate, you may also wish to ensure the clock used for sampling is also ultra stable. This may require a separate supply just for the clock generator.

The best way to evaluate you noise performance is to capture 2^n samples eg 1024. then perform an FFT on the results.
This will reveal if you have any spurious signals getting in there, degrading performance.
Even better to reveal spurious signals is to average multiple FFT's over time.

Simply seeing one digit of noise is not always indicative of a good sampler. 

Thanks. The sampling rate is 10 MSPS.

Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?

[onemilimeter]

Have you considered using a separate voltage source for the ADC, a voltage reference chip can supply a small amount of current to a very high precision, +-2mv and under 10ppm temperature drift can be bought off the shelf? You can also use this to reduce the effect of the rest of the circuit on the voltage supply. Are you putting the input signal through any circuitry before it is fed into the ADC?

Thanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?

[CafeLogic]

Thanks. The sampling rate is 10 MSPS.

LOL, probably something you should mention next time.

Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?

That's the magic of db.

[Chasm]

Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?

That's the magic of db.

Well, that only works if there are not other effects, say parts of the stabilized circuit acting as antenna.

[tyblu]

Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?

I wouldn't do this unless the chip was designed for it (ie: in the datasheet or manufacturer recommended), as there may be feedback stability and current hogging issues.

[CafeLogic]

Thanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?

Generally, you would not power the ADC with a reference. Your very expensive (40$?) 16-bit 10MSPS ADC will have a high and low reference pin. If you decide to use an external reference, you would direct the output to the high pin. Take a look at your datasheet, you can not use the power voltage for reference. On that type of ADC it will always be lower. The stability of the reference is more important than the stability of the power rail.

Out of curiosity, what are you using to process these 20Mbytes/sec worth of data?

[onemilimeter]

Thanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?

Generally, you would not power the ADC with a reference. Your very expensive (40$?) 16-bit 10MSPS ADC will have a high and low reference pin. If you decide to use an external reference, you would direct the output to the high pin. Take a look at your datasheet, you can not use the power voltage for reference. On that type of ADC it will always be lower. The stability of the reference is more important than the stability of the power rail.

Out of curiosity, what are you using to process these 20Mbytes/sec worth of data?

I wish to design a general purpose control platform with similar concept to dSPACE. We've a dSPACE system in our department. I note that the dSPACE system uses several 16-bit 2MSPS ADCs.

[CafeLogic]

I wish to design a general purpose control platform with similar concept to dSPACE. We've a dSPACE system in our department. I note that the dSPACE system uses several 16-bit 2MSPS ADCs.

Does that mean you haven't decided what you are going to process the data with? I mean in the short term, right after it comes out of the ADC.

[onemilimeter]

Does that mean you haven't decided what you are going to process the data with? I mean in the short term, right after it comes out of the ADC.

At the moment, I'm thinking of using TI floating-point processor, either C2000 series or C6000 series.

Thanks.

[CafeLogic]

At the moment, I'm thinking of using TI floating-point processor, either C2000 series or C6000 series.

Nice. You might already be aware but if you use the XDS100 emulator ($79), you can use code composer for free with no limitations.

Good luck with that sounds like a tough project.

[RayJones]

We use a 160MHz C6201 and a 14 bit 40Ms/s ADC.

Swinging dual port memory and DMA is the only way to feed the DSP with the data due to the bus waits that would otherwise be inserted if you used programmed access (EMIF and all that). 

Using DMA still binds up the external bus, but once transferred inside the DSP - no wait states are required and the thing flies

The result data is also DMA'd out.

It does get very complex keeping everything fed and maintaining throughput, but the satisfaction factor is immense.