I agree on the point that usually one does not experiment with expensive prototype boards. I was certainly not suggesting that anybody should re-design a working board based on my experiments. I wouldn't trust a comment from a random forum from somebody completely unknown either. Instead, my experiment was meant for food of thought. Yes, it most certainly does bleed measurably between p5-p6. But between p6-p7 there was no measurable voltage (below 1 µV). That indicates that most current is concentrated near point I1. Plane resistance is not trivial to calculate, thus it is difficult to estimate the resistive coupling without measuring.
I do very well know that higher frequency signals have other sometimes very bizarre coupling ways, like mutual inductance, which is naturally completely absent in case of DC. Inductive coupling is perhaps the most difficult mechanism. Only way to reduce that is to reduce the area between signal and ground and increase distance between two signal loops. However, skin depth dictates that for example at 30 MHz, skin depth is about 12 µm. One could then even put different high frequency signals in each side of the plane and still get almost no cross-coupling. That would also suggest that for high frequencies, splits are not so effective, since coupling could be due to something else than due to the IR drop of aggressor signal. RF guys usually add more grounding or shielding if they need more isolation between signals, I do not know if anyone there uses splits to reduce coupling.
That's why I am also going to do some experiments in the AC domain using a spectrum analyzer with a tracking generator, like I thought above. I'm not personally completely convinced that primary noise coupling mechanism for higher frequencies is through galvanic connection via the ground plane. If it is some other form of coupling, then the slot might possibly cause things to be worse unless the effect is understood. Another thing is that if the chip has two different ground connections, it is usually stated that they should be at the same potential. Now, better the split is, bigger the difference between potentials of these two grounds, thus inter-gnd current (like common-mode) flows through the chip. My primary interest is to understand the coupling mechanisms via measurements, so I can better understand what is the dominant mode of coupling and how much, by what means and where I can degrade the shielding in case of cost reduction situation and still get acceptable results. It also enables to optimize right things in case of performance maximization. It might also well turn out that either is acceptable if properly implemented, i.e. no dramatic difference between these two school of thoughts (my best guess is this).
What also bothers me, is that the "split ground"-chapter in ADC/DAC datasheets seems to be copy&paste'd for decades from one datasheet to another without anyone bothering to actually make measurements and evaluate the results for both ground methods, especially evaluating the external interference immunity. That would be much more convincing than just simple chapter of old statements. Datasheets are not unfortunately always based on physical facts, but industry practices. Although I have been getting impression that newer datasheets do not unconditionally recommend splitting so often, instead they will emphasize the correct parts placement. It is a bit like of "Faraday cage"-advice that is certainly useless unless you know that direct radiation from the circuit in it is the actual source of problem. Usually, it is the common mode ground voltage induced currents in cables what cause EMI failures, rarely the circuit board itself. If all signals entering/exiting the cage are not filtered at the edge, they will conduct the noise outside with ease, thus the cage won't improve the situation at all.
Finally,
ADS5485EVM seems to be using single unified ground plane, and still achieving good results. The statement about grounding seems to be reversed: "The layout features a common ground plane; however, similar performance can be obtained with careful layout using a split ground plane." I can't believe that two different ADC's obey different set of laws of electromagnetism. Same seems to be the case with ADI
AD9650/AD9268/AD9258/AD9251/AD9231/AD9204/AD9269/AD6659 evaluation board.
Regards,
Janne
This is all very interesting, but spurious signals at DC (at least in our application) are dead simple to remove.
Our primary concern was fast switching signals that radiate crap everywhere, they don't even need to be on the same board.
When you deal with signals that exist in the noise, sampling purity is essential.
Perhaps a solid plane could be OK, but when it comes to prototype 8 layers boards, and hand assembly of fine pitch SMD which could cost $1000's to produce in small quantities (factoring in labour), and the need to pull 90dB of usable dynamic range, you pull every trick you know to ensure optimum performance on the first (or second) attempt.
Besides that, you did prove there is bleed beyond the end points.
Yes it is small but if you are using out of band noise, it is highly possible you could expose those small signals as spurious signals.
A cut amputates that bleed effect in a definite known manner.
Redesigning our known good PCB with a solid plane is not beneficial for us to prove it may degrade performance.
Cuts on the ground plane are so easy to place that it is hardly worth the possible "damn I wish I placed those cuts scenario".
Finally, if the chip manufacturer recommended cuts, I know I would be following their advice closer than a primitive DC test conducted in an unknown backyard. 
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