I would add that the loop area must be considered in 3D-fashion, including component leads and connectors/sockets (Mr. Maxwell sees it in this way in the final product!
![Tongue :P](https://www.eevblog.com/forum/Smileys/default/tongue.gif)
). This is often forgotten since layouts are usually examined as 2D drawings and Z-axis is not visible.
Another one is that use source terminated transmission lines (series resistor at source end, contiguous ground plane below the trace, and trace width at least in same order than dielectric thickness, gives you ~75 ohms traces, double trace width gives 50 ohm traces) instead of just random p2p-traces. This won't hurt in EMC sense (even if you wouldn't actually need it), but might cost you more layers to your PCB (step from 2 to 4 is usually the most painful!).
Regards,
Janne