Hehe! It is perfect!
Thank you both,
flolic and
tinhead, for your suggestions to use
proper solder balls to reball the Cyclone III FPGA instead of improvising with a soldering iron and solder wire.
The FPGA 256-Pin
FineLine Ball-Grid Array (FBGA) package has pads of 0.50mm diameter and 1.00mm pitch. Reballing was done by hand (without a stencil), using regular 63/37 alloy solder balls. It took me almost half an hour to do it, by applying gel flux to the cleaned chip pads and pushing every individual solder ball in place before baking the chip using 220°C low velocity hot air to avoid blowing the solder balls away. Surface tension magic did the solder balls alignment.
Before resoldering the FPGA back to the mainboard, in order to power the device up, I will have to verify the connections diagram I have drawn.
__________
Anyway, this is a quick preview of the DS1000X design (that may be partially erroneous since I have not yet drawn the final schematics, to have the whole picture available):
What I find kind of strange in the design is the use of two global buses; a 16-bit wide data bus and a 22-bit wide address bus, interconnecting almost all the stages: The BlackFin DSP to the Spansion boot FLASH RAM & the Hynix system SDRAM chips as well as the Lattice LUT that is a peripherals and memory manager, the Altera FPGA that handles the ADCs and the data acquisition storage Issi SRAM, the Philips USB controller and the optional logic analyser Logic Head.
The FPGA and the Logic Head share of the global address bus is 8-bits wide only, feeding the BlackFin with one screen of data (256 points of two channels data) at a time, on demand.
The DSP feeds the LCD controller with the display data using a local 8-bit wide data bus and talks serially to the Keypad PCB and to a 4Kbit FRAM system preferences memory.
The LUT is in charge of addressing the upper three MSB of the Spansion FLASH RAM and the 18-bit wide Issi SRAM local address bus. It also controls the analog front-end and the analog & triggering section parameters.
The Issi SRAM holds the ADC aquisition data read from & fed to by the FPGA that uses a 4x8-bit wide local data bus to talk to the memory.
The FPGA configuration scheme is set to Active Serial Interface mode (MSEL2:0 = 0b100) and the the BlackFin acts as a passive serial configuration device during FPGA configuration.
Finally, the JTAG ports run on 3.3V
More to come, soon.
-George
EDIT: After a closer examination of the picture, it seems that the C16 solder ball (the third one up, counting from bottom right) needs to be replaced...
EDIT 2: A few corrections and additions.