Cool video!
Couple of comments on some of the structures shown:
The large wires on the around the outside of this circuit is a typical power ring. One would be ground and the other power. Notice the 4x4 array of vias to via down to the next lowest level to pass under the inner ring. Typically wires would have a preferred direction: horizontal wires on odd metal layers and vertical on even (or vice versa) so you would actually see via arrays in the corners of the ring, but it looks like they didn't bother sticking with that rule for the ring itself as they are on the same level all the way around.
Notice the taper down of this wire...again, likely a power or ground wire. The circuits above probably don't need a lot of power, but the groundrules for the bottom metal layer are probably such that it is minimum width (the top metal layers are very thick, and therefore have to be drawn very wide). They via-ed down to the next lowest layer and then were able to run a thinner wire for the rest of the run.
The circuits shown here are pretty interesting. Yes, this looks digital, but "custom" digital as opposed to standard cells that would look far more regular. You can see that the pattern is repeated, but moved up slightly, and wired together in a cascading fashion. I wonder if this is some kind of frequency divider circuit where each stage is basically a flip flop that triggers the next stage on every other transition. If this is CMOS logic, then the PMOS devices are likely where I've outlined in red (the horiztonal wires are probably Metal1 with contacts (vias) down to the diffusion (source/drain) and the gates are in between. The NMOS devices would be where I've highlighted in green. Although this seems like an enormous P/N ratio. If that's the case, then the vertical wire to the left of the green box is probably GND (notice it comes from another power ring type structure above) and the vertical wire to the right of the red box (that looks somewhat translucent like it's on a different layer, but that would be pretty atypical) would be VDD. If this were a true standard cell based design those power and ground busses would be VERY regular and immediately obvious.