I had a look through this Rigol datasheet and there are a few clues wrt the frequency plan there.
http://beyondmeasure.rigoltech.com/acton/attachment/1579/f-0636/1/-/-/-/-/DSG800_DataSheet_EN.pdfeg it lists 5 bands on the second page and this gives a clue as to the division ratio associated with each range.
So I tried to amend my block diagram to include this info. See below for another attempt to produce a frequency plan for the 3GHz version. I still think the same hardware may be used for the 1.5GHz version. However, one thing I can't fully explain yet is the phase noise plot they provide on page 3.
The traces for 3GHz and 1GHz make sense because there is a divide by two on the 1GHz range plus it will use a VCO running at 2GHz. So you can expect the phase noise to be 6dB lower because of the divide by two and maybe another 4 dB lower because of the 2GHz VCO. So the phase noise at 1GHz is about 10dB better than the phase noise at 3GHz.
But I can't explain the phase noise plot at 100MHz.It seems lower than I expected and this implies there are some more stages of division somewhere. Otherwise, I'd expect the phase noise profile at 100MHz to only be a couple of dB lower than the phase noise profile at 1GHz if my block diagram is correct.
The table on page 2 only quotes a divide by 4 for 100MHz so this agrees with my block doagram but this means a cleanup of (only) about 12dB wrt the phase noise at 3GHz and then the BFO is used to downconvert to 100MHz.
So something doesn't add up here because the cleanup at 100MHz is more like 24dB. I'll try and spend some time looking at the other side of the RF board to try and spot an extra divider (divide by 16?) and an associated lowpass filter. The phase noise plot suggests that 100MHz is achieved with a simple divide by 16 rather than the 'divide by 4 plus BFO' shown in my block diagram.