Author Topic: EEVblog #801 - How To Design A Digital Clock  (Read 92658 times)

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Online bitwelder

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #100 on: September 25, 2015, 06:10:55 am »
Great video, Dave!  :-+
Not that microcontroller rubbish, thankyouverymuch.
 

Offline sbprojects

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #101 on: September 25, 2015, 06:16:37 am »
As it so happens I have build my own 24 hour CMOS clock a few months ago, just for fun. The parts had been sleeping in my junk box for over 30 years.
Check out the detailed description of it if  you like at http://www.sbprojects.net/projects/cmosclock/

« Last Edit: September 25, 2015, 08:39:16 am by sbprojects »
 

Offline Howardlong

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #102 on: September 25, 2015, 06:57:58 am »
Just a quick question, on the resetting of the 4026's how are you using the carry before it has finished its count?

IIRC (from 25 years ago!) the carry will still work when you force the reset.

There was a bone of contention back in the day (when I did my TTL clock) about using ripple counter outputs on non-synchronous resets because it is possible, if the data sheets are taken literally, that the counter may not fully reset on the required condition combination. As no minimum propagation delays are generally quoted,  technically they "should" be considered to be zero. Of course, in reality this was not what happened and the practice tying outputs to reset inputs this was very common because it worked.

On the clock I made, not having enough experience, I chose to do it the hard way, and cobbled together all sorts of SSI logic to make it work technically correctly within the data sheet spec, but it added a fair bit of extra complication. But as a 12yo, it taught me an awful lot about digital design logic, reading datasheets, and being analytical.

The 4026 is a Johnson counter (plus decode) rather than a ripple counter but the same concepts still apply, that it is possible that the counter may end up in an undefined state if the reset pulse is too short. Again, of course, in practice there was always sufficient propagation delay between input and output as well as "give" in the real life specs that this worked: use of the technique was very common.
 

Offline krivx

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #103 on: September 25, 2015, 07:12:40 am »
Dave, did you not use PNPs at the time?

Sure, but NPN's worked just fine.

Cheers Dave. I ask because I know I tended to "think in NPN" (and still do, to some extent) and will often grab NPNs first even if a PNP circuit could do the same thing with fewer parts.
 

Offline SeanB

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #104 on: September 25, 2015, 07:52:47 am »
The simplest way to ensure that you meet the minimum reset pulse length is to use a capacitor of around 10n  across the DTL logic gate, which means it has a built in delay on going high so meeting the required width. Going low is fast, but a delay going high. Might cause an issue if you are using a ripple counter with a fast clock input ( clock period less than reset pulse width) where you might get an incorrect count as some gates reset threshold is slightly different from the others so they might reset as a clock arrives and miscount, but for low frequency or with a short pulse no worry.

You can see that on Dave's board.
 

Online tggzzz

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #105 on: September 25, 2015, 08:01:20 am »
I made a clock back in High School that is still running to this day (~10 years old) that I did a write-up for way back when located here

Mine 1973-ish clock still runs, and I updated it to become more "interesting": https://entertaininghacks.wordpress.com/2015/02/23/vetinari-digital-clock/
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Online tggzzz

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #106 on: September 25, 2015, 08:04:20 am »
The frequency of power cuts was also a large part of my reasoning behind getting a butane soldering iron many years ago. The idea being it would give me something to do in a power cut. There's been lots of power cuts since and I don't think I've ever used the butane iron during one, so that turned out well. Nowadays I mostly use it to shrink heatshrink.

I remember using a soldering iron that was a lump of copper that you heated up on the gas stove - but not for semiconductor-scale things. It would probably still be useful where large amounts of heat are needed, e.g. soldering two sheets of copper together when making a shield. I'll try and find it sometime.
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
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Offline Stupid Beard

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #107 on: September 25, 2015, 08:05:15 am »
Blimey, where do you live? The only time we had a power cut since the glory days of trade unions in the 70's was a year ago when I noticed my server powering down and rebooting and then the house lights dimming randomly.

I'm in West Sussex. I think http://www.bbc.co.uk/news/uk-25515310 is the christmas one I was thinking of, and it was the worst one that we've had in a long time. We do have the odd 1 or 2 every year or two when there's bad storms, but they usually only last around a day.

On a slightly more on topic note, I found my old clock project. Just hooked it up to my bench supply and it still works. It's PIC based rather than CMOS, sorry about that. I lashed it together over a few days whilst bored one christmas many years ago after finding a bit of MDF in the cupboard. It's funny where inspiration comes from sometimes.



The unlit LED on the outer ring indicates the hour, the center LEDs are the minutes in binary (blue flashes once per second, green is the 10s of minutes, orangey red the rest). I nicknamed it the clock of doom because the minutes LEDs were initially so damn bright you couldn't actually look at the clock. I remember trying to add PWM for the LEDs, then realising I fucked up and did PFM instead and never got around to fixing it.

The two extra holes on the front were going to be for an LDR (for auto dimming the LEDs) and the DS1820, but I never got around to adding the LDR and I made the leads for the DS1820 far too short and couldn't be arsed to fix it.



It uses a PIC18F448 (which was seriously overkill), a DS1307 with inappropriately loaded crystal, and a DS1820 for the temperature. I was actually surprised when I turned it back on to find that it was only 5 minutes fast. I think it has been a couple of years since I adjusted the time.

The hours LEDs are charlieplexed and the minutes LEDs are just connected straight to GPIO pins. The debouncing on the buttons is terrible so they frequently miss presses. They do let you set the time, however, as well as turn off the (extremely annoying) flashing blue LED, the seconds display and the temperature.

For years I've been meaning to redo this project properly and fix all it's many quirks and idiotic mistakes. Maybe I'll finally get around to it; the discrete clock was particularly inspiring.
 

Offline SeanB

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #108 on: September 25, 2015, 08:21:20 am »
I have seen universal clock chips before while browsing data sheets.
I think it is silly for you to just catigorically say I am wrong.

 |O
Again, I'm not the one making claims!
You made a claim (well, you backed up someone else's claim, saying it's "factual") that the clock counted down. You get to prove it, that's how it works.
I'm not saying it's not possible, but it seems unlikely. It's a reasonable position to hold until you actually provide evidence or proof.

You said, and I quote:
Quote
Good Job, all factual.
in response to these supposed facts:
Quote
2.  The clock was altered into a countdown timer, rather than an RTC.
3.  Said clock/timer was executing an active countdown when the incident occurred.

Prove it.

http://www.nteinc.com/specs/2000to2099/pdf/nte2062.pdf

Datasheet of a pretty common clock chip. Page 2 table 5 shows how to get the display to show a countdown timer on the sleep function.

On some clocks that use a diode matrix to change the arrangement of the switches ( you have a time set switch to press first) You need to have time set pressed first along with alarm set and sleep to get this display to show, and an active sleep running.
 

Offline GK

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #109 on: September 25, 2015, 09:06:05 am »
Here's my teen clock; just pulled from the junkbox. I'm surprised it's still so intact.

HH.MM.SS display, 74LS90+74LS47 for each digit. A 2MHz XTAL oscillator based on a single 4011 gate is divided down to 1Hz by six 4017 decade counters and 1/2 a 4013 DFF wired to toggle in series. 555 timers wired as monostables to de-bounce the time-setting push-buttons. Discrete RTL gates for handling the manual-set functions.

The 2MHz XTAL doesn't appear to be on the board anymore. I abandoned this project and never packaged it because I could never get it to keep accurate time - it would loose several minutes per day IIRC. I didn't know enough about XTAL loading/capacitance specifications at the time and the trimmer cap visible was just some random (unknown value) that I salvaged from a radio or something. I do recall soldering in different kinds of values. This was before the internet and all I had for reference was my Dick Smith Funway and Tandy Forrest M Mimms books.

My workshop is currently without a clock. Hmmm.....I think that I should finally fix the oscillator properly and commission this clock by fixing the wiring and mounting it on a wall-hanging board with a sheet of perspex over the front.
« Last Edit: September 25, 2015, 09:21:22 am by GK »
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Offline SeanB

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #110 on: September 25, 2015, 09:14:39 am »
Probably the biggest thing leading to the poor time keeping is the lack of decoupling capacitors. Those are definitely needed on the oscillator to keep it stable, as the fast edges will affect thresholds on the gates and leads to jitter on the clock. Also a thick short wire from the crystal capacitors to the Vss pin and a similar one on the longer lead of the supply decoupling cap. Might even benefit from the Vdd supply being fed through a ferrite bead and a decoupling capacitor before and after it.

Slap a few across random counters, a 10uF electrolytic on the input 5v rail and it should work better.

Other than that it should be nice to have on the wall.
 

Offline GK

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #111 on: September 25, 2015, 09:16:18 am »
Yes, it appears to have rather spartan power supply decoupling.
« Last Edit: September 25, 2015, 09:18:15 am by GK »
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Offline Fungus

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #112 on: September 25, 2015, 10:25:41 am »
http://www.nteinc.com/specs/2000to2099/pdf/nte2062.pdf

Datasheet of a pretty common clock chip. Page 2 table 5 shows how to get the display to show a countdown timer on the sleep function.

 :palm:

Yes, but was the clock in question actually modified that way? Was it counting down when he took it to school?
 

Offline f4eru

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #113 on: September 25, 2015, 11:05:44 am »
Hello Dave,

Nice optimizations and tricks in your clock :)

For the hour counting, I would have used half a 4520 wired as modulo 12 counter, and a similar bit of glue logic to convert that to the needed 1,5 digit signals...
This way you could replace the 4013 used for the AM/PM by the second half of that 4520 (with no reset, just use the LSB and let it count modulo 16) -> spare one IC.

Or in fact, I would in fact have made a 24 hour clock, as this format is more common here than AM/PM...

When I was young, I made a LED clock with a bunch of leds arranged in two concentric rings.
I also brought it to school, and no one freaked out.
It was made on two self made PCBs with hand drawn traces + decals directly on copper clad ..... Wow, when I think about that .....
The design came from a elektor or elex.

Elex was a very very funny electronics magazine with a lot of funny illustrations :

look at p4/5 here for a nice story how 7 segment displays are organized :))) :

http://docsenstock.free.fr/a/elex/LX1989-13+.pdf

(yeah it's french, but you will understand the story from the pictures anyway.)
Wanted : complete scans of the "Elex" magazines ....

At the lab I've never had a single blackout (don't know about nights when not here)
Your clock has a nice side effect feature of detecting power losses in the night by resetting :)

Blah, it uses one of those new-fangled integrated clock chips, sacrilege!
Yep, that IC is definitely not in production any more, whereas all the logic IC you used can be bought for 10-50cent today.

a genius bomb-maker who goes to the extreme of reverse engineering a fucking radio alarm clock instead of going with a much simpler 555 timer or Arduino or the good old mechanical switch
A 555 is not a good idea for a bomb timer, or any similar long timing : at long times it becomes unreliable because of the leakage current overcoming the capacitive charge current.
I suggest using a 4060 with a much faster oscillator and a big division factor instead.

« Last Edit: September 25, 2015, 11:23:07 am by f4eru »
 

Offline johnwa

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #114 on: September 25, 2015, 11:34:14 am »
Nice clock Dave! I found the circuit vaguely familiar as I was watching, and, after a bit of rummaging through old magazines, I think I have tracked down what it reminded me of: the Talking Electronics clock project. This appears to use the same count-to-12 arrangement, though the display format is different. Perhaps this might have been an inspiration for you - I know you were a big fan of Colin's work.

The 10Hz fast set is a nice touch - I think some of the designs using stray 50Hz might have been a bit temperamental.

 

Offline zapta

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #115 on: September 25, 2015, 11:58:27 am »
Err, no, that's a just a throw-away line because of recent events.
I did not make this video for Ahmed.

This explains the lack of detonator output in your design.

;-)
 

Offline Ed.Kloonk

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #116 on: September 25, 2015, 12:21:03 pm »
Must have been awful waiting 10,12 and 24 hours to debug that hour circuit.

I believe we don't have precise power frequency anymore. I recall in the news a while back that they were abandoning the daily clock watching/adjustment at the power stations.

Does anyone know more about this?
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Offline AF6LJ

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #117 on: September 25, 2015, 12:31:07 pm »
I have seen universal clock chips before while browsing data sheets.
I think it is silly for you to just catigorically say I am wrong.

Men can't live with them, can't live with out them.

Dude, whether it is possible or not is irrelevant. Conspiracies are being stated as fact. On one had, the conspiracy nutters are saying well he didn't design anything and just disassembled a clock and reassembled in another receptacle to discredit him technically.
First off I am not a DUDE, I am female. Perhaps you should check people's profiles once and a while.
And no I am not going to address your comment, not worth the bandwidth here.
Quote
Then the very next point, to continue the conspiracy theory, saying how it had been modified into a countdown timer. Even if it had, then it would require more than just disassembly.
And you have evidence the clock was only disassembled? please lets see it.
Quote

You can't have it both ways, but more importantly you can't state conspiracy as fact.
When you have provable facts please come back with them and their sources.
Sue AF6LJ
 

Offline AF6LJ

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #118 on: September 25, 2015, 12:32:57 pm »
I have seen universal clock chips before while browsing data sheets.
I think it is silly for you to just catigorically say I am wrong.

 |O
Again, I'm not the one making claims!
You made a claim (well, you backed up someone else's claim, saying it's "factual") that the clock counted down. You get to prove it, that's how it works.
I'm not saying it's not possible, but it seems unlikely. It's a reasonable position to hold until you actually provide evidence or proof.

You said, and I quote:
Quote
Good Job, all factual.
in response to these supposed facts:
Quote
2.  The clock was altered into a countdown timer, rather than an RTC.
3.  Said clock/timer was executing an active countdown when the incident occurred.

Prove it.
I am simply backing up what was reported in the news. You are making the claim I am somehow wrong without anything to back it up.
But hay..
I get it.
Sue AF6LJ
 

Offline AF6LJ

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #119 on: September 25, 2015, 12:40:07 pm »
I have seen universal clock chips before while browsing data sheets.
I think it is silly for you to just catigorically say I am wrong.

 |O
Again, I'm not the one making claims!
You made a claim (well, you backed up someone else's claim, saying it's "factual") that the clock counted down. You get to prove it, that's how it works.
I'm not saying it's not possible, but it seems unlikely. It's a reasonable position to hold until you actually provide evidence or proof.

You said, and I quote:
Quote
Good Job, all factual.
in response to these supposed facts:
Quote
2.  The clock was altered into a countdown timer, rather than an RTC.
3.  Said clock/timer was executing an active countdown when the incident occurred.

Prove it.

http://www.nteinc.com/specs/2000to2099/pdf/nte2062.pdf

Datasheet of a pretty common clock chip. Page 2 table 5 shows how to get the display to show a countdown timer on the sleep function.

On some clocks that use a diode matrix to change the arrangement of the switches ( you have a time set switch to press first) You need to have time set pressed first along with alarm set and sleep to get this display to show, and an active sleep running.

Thank You...
Sue AF6LJ
 

Offline f4eru

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #120 on: September 25, 2015, 12:40:38 pm »
It depends heavily on how the grid is managed.

Here in Europe, a frequency is guaranteed at normal times, there is very little variation, due to phase sync of a big number of grids.
The reason is that there is still a lot of domestic appliances keeping time based on the grid.
Advantage is the drift is limited to, say, 30s. With a quartz based clock, the drift is not limited, and you have to trim the clock time every few months.
Drawback is the non deterministic drift. 50/60 Hz automatic switching can be done if the uC has an internal clock with 5% frequency accuracy.


https://www.swissgrid.ch/swissgrid/en/home/experts/topics/frequency.html
https://en.wikipedia.org/wiki/Synchronous_grid_of_Continental_Europe
http://wwwhome.cs.utwente.nl/~ptdeboer/misc/mains.html


Now, if the whole synchronized grid is in an emergency situation, or if one part falls out of sync, there could be a significant frequency deviation
This frequency deviation is how the power companies decide to do load shedding....
See for example here ( in german) http://blog.fefe.de/?ts=aba55ed4

One funny thing to notice is that the UK is, as usual, not playing ball with the rest of the EU, so their grid needs more reserve power ( they can exchange a "little bit" of power to the EU through inverters ), and this is one of the reasons (along with crumbling infrastructure) that they have a lot more power outages.

One of the problematic countries is Japan, separated in two zones : 50 and 60 Hz... These two zones are also connected by HVDC inverters
« Last Edit: September 25, 2015, 01:05:27 pm by f4eru »
 

Offline rdl

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #121 on: September 25, 2015, 02:09:49 pm »
I found my old unfinished clock project in the closet. Plugged it in and it started fine. It looks like the hours counting logic is missing which would make sense because I think that's what I was working on when I shelved it 2 years ago. I'm thinking now that maybe I'll forget about the 12/24 switching and just finish it up as 12 hour am/pm because I know I had that much working correctly.
 

Offline zapta

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #122 on: September 25, 2015, 03:27:34 pm »
Here in Europe, a frequency is guaranteed at normal times, there is very little variation, due to phase sync of a big number of grids.
The reason is that there is still a lot of domestic appliances keeping time based on the grid.
Advantage is the drift is limited to, say, 30s. With a quartz based clock, the drift is not limited, and you have to trim the clock time every few months.
Drawback is the non deterministic drift. 50/60 Hz automatic switching can be done if the uC has an internal clock with 5% frequency accuracy.

How do they sync between all the power stations connected to the same grid?  Is there some master that determines the frequency/phase and everybody else locks to it?  Or, is it some symmetric system when they all lock to each other and a way that guarantees convergence?

It seems to be a very challanging problem, considering the scale and complexities of the grid and the energy levels involved.
 

Online tggzzz

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #123 on: September 25, 2015, 03:46:38 pm »
Here in Europe, a frequency is guaranteed at normal times, there is very little variation, due to phase sync of a big number of grids.
The reason is that there is still a lot of domestic appliances keeping time based on the grid.
Advantage is the drift is limited to, say, 30s. With a quartz based clock, the drift is not limited, and you have to trim the clock time every few months.
Drawback is the non deterministic drift. 50/60 Hz automatic switching can be done if the uC has an internal clock with 5% frequency accuracy.

How do they sync between all the power stations connected to the same grid?  Is there some master that determines the frequency/phase and everybody else locks to it?  Or, is it some symmetric system when they all lock to each other and a way that guarantees convergence?

It seems to be a very challanging problem, considering the scale and complexities of the grid and the energy levels involved.

It is challenging. For one station re-attaching to a functioning grid, "all" it has to do it is sync with the cables going past the station.

The real problems would arise in a complete grid failure, not least because a power station needs an electricity supply to "get going" in the first place! This is the so-called "black start" problem: https://en.wikipedia.org/wiki/Black_start 

In the UK hydro plants are designated for black start capacity, e.g. https://en.wikipedia.org/wiki/Cruachan_Power_Station
There are lies, damned lies, statistics - and ADC/DAC specs.
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Offline LabSpokane

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Re: EEVblog #801 - How To Design A Digital Clock
« Reply #124 on: September 25, 2015, 03:49:03 pm »
Here in Europe, a frequency is guaranteed at normal times, there is very little variation, due to phase sync of a big number of grids.
The reason is that there is still a lot of domestic appliances keeping time based on the grid.
Advantage is the drift is limited to, say, 30s. With a quartz based clock, the drift is not limited, and you have to trim the clock time every few months.
Drawback is the non deterministic drift. 50/60 Hz automatic switching can be done if the uC has an internal clock with 5% frequency accuracy.

How do they sync between all the power stations connected to the same grid?  Is there some master that determines the frequency/phase and everybody else locks to it?  Or, is it some symmetric system when they all lock to each other and a way that guarantees convergence?

It seems to be a very challanging problem, considering the scale and complexities of the grid and the energy levels involved.

It is a very challenging problem.  Phase synchronization issues can cause very large blackouts.  For power transmission, the phasor is used to convey magnitude and phase of the real and complex part of voltage and current in the form:



There is a master clock for each grid authority.  In the US we have three major grids:  West, East, and Texas ERCOT. 

In the US, we are moving to using synchrophasors http://energy.gov/articles/how-synchrophasors-are-bringing-grid-21st-century in order synchronize the phase angles between generation stations.  Synchrophasors are referenced to a common clock such as GPS and then transmitted to a common, coordinating authority.  Schweitzer Labs, has a good primer as well as live data to view:

https://www.selinc.com/synchrophasors/

« Last Edit: September 25, 2015, 03:53:04 pm by LabSpokane »
 


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