The SPI bus was probed. For comparison, here are the bytes from the beta for the AD4360-7 PLL registers:
THanks again, MarkL. Here is my analysis of it.
- no change in PFD frequency of 2.5MHz from Beta
- no change in lock detect setting of Digital Lock Detect (High), and as you said, the PLL is still not locked and as the result puts out garbage
- change in Band Select bits, now properly set.
See my reply #575 earlier in this thread for details
- no change in Antiback slash pulse of 6nS from Beta, change from original firmware (3nS). Useless because only has effect when PLL is in locked state
-no change in charge pump current of 0.31mA. The part's specifications are based on 2.5mA current in the Datasheet, but Rigol did not read it anyway.
-change in Core Power Level from 20mA in Beta to 15mA back as it was in original firmware. Same as before, outside of the part manufacturer specification and could be the culprit of all this mess beside the invalid loop filter.
See my reply #582 earlier in this thread for details. ADI treats this setting critical ("...
In particular check the core power, it is critical that this be set to 5 mA") but that was of no meaning to Rigol.
Providing the Core Power Level was correctly set to 5mA, simulation shows that with the above settings and existing loop filter the phase margin value is 36 degrees which is a fair cry from recommended 45 degrees an most PLL book, the others recommend 50 degrees minimum. Therefore do not expect Rigol's PLL be stable to begin with. Cranking up the Core Power Level to 15mA makes all and any thing unpredictable, which is what we all are witnessing in this case.